Research On High Speed Signal Simulation Technology In Serial Link

In today's booming semiconductor process,the chip is highly integrated,and its highest signal interface rate has reached tens of gigahertz,while the development of printed circuit board(PCB)-related processes is relatively slow,and it cannot show Moore's Law like semiconductor processes.The development trend matches the chip design process.High-speed signals are transmitted over long distances on high-loss links on the PCB.Signal integrity(SI)problems caused by losses,reflections,crosstalk,etc.,can cause signal distortion to a large extent,and cannot be completely restored at each load end.Signal on the driver side.With the rapid and rapid expansion of the Internet data volume at this stage,the research and design of high-speed communication equipment such as routers and switches is very important.As a core part,the high-speed serial link has become a major technical difficulty.This thesis is based on the SI theory and the 3D modeling and overall optimization design of key components of high-speed serial links based on the CEI-25G-LR standard.Completed the analysis of high-speed signal simulation technology,the main work of thesis is based on the precise modeling method of serial link research.Combined with the high-speed serial protocol standard,differential transmission lines,PCB stackups,differential vias,and AC coupling capacitors,the design parameters are given,and finally the performance index of the whole channel is reached,which provides a important reference for the actual engineering design.The main work and innovations of the thesis are as follows:(1)The link is classified and the basic parameters of the differential transmission line are determinedThrough the hierarchical processing of the links,the basic parameters of the differential transmission line are determined,the actual situation of the loss and crosstalk in different reference planes is simulated,and the PCB stack-up design is given.(2)The parametric model of differential via and AC coupling capacitor structure is establishedParametric modeling of differential through-hole structure is carried out,and the influence of parasitic effect on the rise time of actual circuit is analyzed through the designing of through-hole parameters.At the same time,the residual pile removal by back drilling and structural optimization of reverse pad are carried out for differential through-hole.Analysis of simulation on the impact of channel performance is carried out,and the corresponding eye chart analysis changes are given.Parametric modeling of the structure of AC coupling anti-pad void area and analysis with eye diagrams,can determine the placement position of the AC coupling capacitor in the actual circuit.(3)Cascade the high-speed serial link and establish the equivalent circuit model for the whole channelIt proposes an overall cascade analysis method for the cross backplane link,establish an equivalent circuit model for the whole channel,simulate and analyze the time domain reflection characteristics,and cascade the S-parameter template to obtain the differential loss characteristics of the passive channel.The actual differential back loss of the cross backplane link is not less than-12 dB within the frequency of 6.45 GHz,and the differential insertion loss is not less than-30 dB within 15 GHz,and the overall curve meets the design requirements.Finally,the 64B66B random bit stream required by 100G Ethernet is added,and active optimization simulation analysis is performed on the entire channel.The solution difference between the bit-by-bit mode and the statistical eye diagram mode is compared,and the appropriate simulation bit stream length is determined.And three equalization methods are used to optimize the channel transmission performance to obtain the final eye diagram and channel response curve.