Design And Implementation Of High-speed Bit Error Rate Tester Based On STM32

The development of society has brougth us more information, and the carrier of information transmission is continually being updated. At present,the electrical signal transmission and communication system has been gradually instead by the light which can also be the carrier of transmission and communication system. Because of the advantages such as large transmission capacity, fast speed, strong anti-interference ability, etc, optical communication has become into the industry trend. The transmission speed of optical modules and active optical cables is being faster, but in high-speed optical communication systems, bit errors must exist. So, it is important for verifying the reliability of optical communication systems to test the bit error rate.In this paper, for the test requirements of a large number of 10 Gbps optical modules, a four channel high-speed bit error rate tester(BERT) has been developed. It is used for testing the optical transceiver module of SFP?XFP, which transmit at the speed between 9.953 Gbps to 11.318 Gbps, it is also compatible with Ethernet?Fiber Channel?SDH and Infiniband. It supports a variety of PRBS code output with 10 bit displayed, and its four channels can test four different 10 Gbps optical modules or one AOC which owns four 10 Gbps channels itself at the same time. Also, it has a touch screen interface which will benefit the large number testing of optical modules.The main work of this paper is as follows:1.By analizing how high-speed BERT works and the requirements for large number testing, it proposed several realization methods for testing system, then found the best one by comparing each other, and proposed what performance should BERT need.2.It has elaborated four channel high-speed BERT implementation which is based on STM32, VSC8248 and GN2010 E. It completed the schematic design of hardware for functional modules and signal optimization modules based on the main chips. Also, it has completed high-speed PCB design under the theory of high-speed signal integrity.3.It has developed the software system, and designed the human-computer interface after achieving the goal of bit error rate testing.4.It has tested the sender, receiver and human-computer interface. The peak to peak level of transmitter is about 800 mV, and its rise time is lower than 40 ps with the signal total jitter TJ lower than 0.28 UI, which meets the demand of 10 G Ethernet, SDH. The receiver can accomplish bit error rate test. Finished with Tektronix BERT comparison test, by actual test of optical modules, the reliability verification of the instrument is completed.