Development Of High Speed Bit Error Rate Tester Based On FPGA

BERT is used in detecting for reliability of a communication system. It is an im-portant instrument which can verify the data transfer quality. High speed BERT used in synthesizing and processing terminal system of the earth station is studied and devel-oped in this project. It is implemented by adopting digital multiplex and FPGA. Its data rate has exceeded 300Mbps.In this thesis, the second chapter discusses the correlative theory about digital communication and multiplex technology. The third chapter discusses transmitter's de-sign scheme of high speed BERT. The fourth chapter introduces the designing and im-plementing about the hardware of high speed BERT, and gives some actual design cir-cuits. The fifth chapter introduces the designing and implementing about the software of high speed BERT, and gives the simulation results of some program blocks and top block. The testing parameters are given in the sixth chapter. In conclusion, this thesis summarizes the project's process of the study and development, and also brings forward some tasks which are going to be done.In this project, the kernel chip is XC2VP4, which is a platform FPGA manufac-tured by Xilinx Co. ISE7.1i Foundation which is the latest and integrated EDA devel-oping tool is used in the software developing. ModelSim SE6.0 and ISE Simulator are the simulation tools. Synplify Pro8.1 and XST are the synthesis tools. All of high speed signals are Low Voltage Differential Signals (LVDS). The debugging of hardware and software has achieved success. Parameters of high speed BERT have met the design requirement. High speed BERT which has been used in bit error rate test in the synthe-sizing and processing terminal system of the earth station has acquired a good effect.