Research And Design Of A High Precision Succesive Approximation Analog-to-digital Converter

As an interface between analog circuits and digital circuits,successive approximation analog-to-digital converter(SAR ADC)has medium conversion accuracy and medium conversion speed and can be pack aged in smaller sizes,which is suitable for the strict requirements on the overall circuit size and plays a very important role in the signal processing of the entire So C.With the rapid development of the application of portable electronic terminal equipment,the comprehensive perfor mance requirements of accuracy,speed and power consumption of SAR ADC are constantly increasing in the fields of w ireless communications,image video transmission and radar monitoring and control.However,in general,the precision range of SAR ADC is 8 to 16 bits.And,as it's accuracy increases,the power consumption will also increase.In order to solve the problem of insufficient accuracy of SAR ADC,a 14-bit precision SAR ADC is designed and has a power-saving mode.The core circuit module mainly includes digital-to-analog converter(DAC),comparator and sequential logic control.In the DAC circuit,an improved pa rallel segmented capacitor architecture is used to divide the capacitor array into high and low groups symmetrically arranged up and down.The capacitor array is respectively coupled to the non-inverting input terminal and the inverting input terminal of t he comparator.In the comparator design,a high-precision dynamic comparator is designed by using the structure of cascaded pre-amplifier and regenerative comparator.At the same time,it has good low-power characteristics.In the logic control circuit,the use of dynamic logic control based on the CMOS unit design,and the sampling circuit is integrated into the logic control circui t with sampling enable control,which can achieve different conversion speed.Only the upper capacitor array to participate in the sampling process,thus increasing the overall system speed of the circuit,also reducing the power consumption.The SAR ADC designed in this paper is powered by 1.5 V and 3.3 V two supply voltages which uses the HHGRACE 0.11 mm 2P4 M CMOS process tt corner and the clock frequency is 2 MHz.The simulation results by Cadence Spectre show that the conversion rate of the SAR ADC can reach 121 Ksps.The signal-to-noise ratio is 72.65 d B.The spurious free dynamic range is 80.26 d B.The effective bit is 11.78.The total harmonic distortion is-72.75 d B.The average power consumption is about 0.22mW.