Design Of10Bit10MHz SAR ADC

The successive approximation analog-to-digital converter (SAR ADC) in its low power consumption and low area advantages, and is easy to be controlled through the clock conversion rate and power consumption, now it has been widely used in industrial control and medical instrument. With the rapid development of today’s system on chip(SOC) and portable devices, the SAR ADC will be dominant in the low power consumption make it get more extensive application in the future.In this paper, thinking from the further reducing power consumption, through improving the traditional successive approximation ADC digital control structure, in order to making a simple control logic at the same time to reducing power consumption. In the new structure we used the capacitor plus plate sampling structure, one-way switch capacitor array. And the comparator also designs to reducing feedback noise. The overall layout of analog and digital parts are made of full custom design, with each part of the circuit is optimized for better. This design use of SMIC0.18CMOS technology, designed and completeda10bit,10MHz SAR ADC on chip, The simulation analysis was performed on the cadence platform, simulation results show that in the10MHz sampling rate the wholecircuit power consumption of5.8mW, the FOM value is0.8pj/conv. SNDRachieve59dB, which effectively reached9.5bit, the chip area is0.6mm2. Compared with the traditional structure of the new structure, logic has greatly simplified and the power consumption is also decreased, and the simulation results verified the structure of logic optimization and power optimization scheme.