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Design Of A Low Power SAR ADC Applicated In RFID

Posted on:2018-01-01Degree:MasterType:Thesis
Country:ChinaCandidate:W L LeiFull Text:PDF
GTID:2428330566451484Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of radio frequency identification(RFID)technology and the design combinating with sensor technology,RFID gains a extensive application prospects in biomedical,Internet of things,high-end manufacturing,real-time logistics chain management and other fields.Designing a SAR ADC with low power consumption,small area and high precision is essential to build an RFID system that identifies the environmental information of an object.In this paper,through research and analysis of the SAR ADC system,a 9-bit 40 KS / s charge redistribution successive approximation analog-to-digital converter is designed based on SMIC 0.18?m CMOS process.A novel DAC switching scheme based on common mode voltage switching strategy and voltage level-shift technology is proposed.No need to alter the switches in the capacitance array on judging the highest and the second highest bit,with a 98.4% reduction in the dynamic power consumption of the capacitance array and a 75% decrease in the unit capacitance quantity compared to the traditional type.The feasibility of the scheme is verified by repectively modeling the ideal and capacitive-mismatch systems in Matlab.A CMOS complementary switch is applied as the sampling circuit,having accrucy improved effectively.A sub-capacitor array and control logic circuit are implemented to calibrate the highest bit capacitance in the main capacitor array.A method of correcting the input offset voltage of the dynamic comparator by adjusting the output load capacitance is implemented.A SAR digital logic control circuit is implemented in Verilog based on synchronization timing logic.Cadence is applied to simulate the designed SAR ADC system circuit and the results are listed as follows: The spurious-free dynamic range SFDR is 69.06 dB.The signal to noise and distortion ratio SNDR is 54.86 dB.The effective number of bits ENOB is 8.82 bits.The differential nonlinear DNL and the integral nonlinear INL are 0.33/-0.33 LSB and 1.31/-0.13 LSB,respectively.
Keywords/Search Tags:Analog-to-digitalconverter, charge redistribution, switching procedure, calibration, synchronous sequential logic
PDF Full Text Request
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