Research On Coding Compression Technique Based On Low Power System-on-a Chip Test

With microelectronics technology and Semiconductor technique approaching the era of deep sub-micron system, System-on-a chip has become the main trend on the development of large scale integrated circuits. With circuit size, complexity and operating frequency rising, high speed testing for So C often occupies a lot of test bandwidth and puts forward a great challenge to the hardware resources of automatic test equipment. In addition, it takes a long test set to meet the requirements of the test coverage, which consumes a large amount of hardware resources and increase storage capacity requirements. Therefore, test data compression and low power test technology are very important to the development of integrated circuit industry.This dissertation focuses on So C low power test and test data compression technology. The specific work includes the following three aspects:1. This dissertation analyzes the research background and developing trend of test data compression and low power test technology for So C, expounds the basic principle?main works and technical challenge for System-on-a chip testing. Systematically introduces fault modeling, test pattern generation and scan testing.2. This dissertation introduces two kind low power test programs systems on chip. On the basis of this, puts forward a low power test set preprocess method. It involves: don't care bits second ordering, hamming distance second ordering, test set second transpose, and don't care bits minimum transition filling. It also designs the corresponding decompression structure and finite state machine. At last, corresponding experimental simulation and verification has been carried out according to MINTEST from International ISCAS'89 benchmark circuits. The experimental results show that high coding compression efficiency and low power dissipation are obtained after the low power test set preprocessing method.3. This dissertation introduces several kind of common test data encoding method. On the basis of this, this dissertation first puts forward a test data compression method based on alternating statistic run-length code. Introduces the basic principle of ASRL coding rules and the dynamic 4m don't care bits filling scheme. Also designs the corresponding decompression structure and the finite state machine. Finally, some circuit verification and experiment simulation are carried out for the MINTEST test set of ISCAS' 89 benchmark circuit. The result shows that, ASRL coding method has advantage in compression efficiency, test power consumption, test application time and area overhead.4. This dissertation further puts forward the extended counting compatibility pattern run length coding compression method for low power test set, also puts forward the ECCPRL coding rule and the don't care bit filling scheme, gives an example to show up ECCPRL coding ideas. Finally, some circuit verification and experiment simulation are carried out for MINTEST test set of ISCAS'89 international standard circuit.Finally, in view of existing problems and some technical bottlenecks in the system on chip multi-core parallel scan test, the dissertation analyzes and looks forward to the future research work, such as the So C test hardware cost evaluation, test controller design, test method, and so on.