To Design A Pixel-Level Cyclic ADC For X-ray Detector

X-ray detectors are devices which can convert invisible X-ray radiation energy of universe into digital signals.Because X-ray has strong penetration,X-ray detectors are widely used in medical imaging,customs inspection and cosmic observation.The dominant units of X-ray detector are signal detection circuit,data readout circuit and digital signal processing module.The pixel-level digital readout circuit is different from chip-level digital readout circuit and column-level digital readout circuit for which the pixel-level digital readout circuit needs pixel units matching.An hxh pixel array needs hxh data readout circuit which pose a challenge to the design of readout circuit in area and power comsumption.Analog to digital converter(ADC)connects analog signals with digital signals in pixel-level readout circuits,similarly,low power and small area will be a difficult task on research and design of pixel-level analog to digital converter.In order to meet the requirements of small area and low power ADC for X-ray detector digital readout circuit of the 10kHz frame frequency and 64x64 pixel array,first the ideal model of ADC has been set up on this paper,and low power and small area ADC has been designed by adopting the cyclic analog to digital converter(Cyclic ADC)architecture.Then some nonideal factor has been added in ideal model for set up nonideal model,and the influence of thermal noise and capacitance mismatch on ADC have been quantitatively analyzed.After the architecture of ADC has been determined,a 12bit and sampling frequency of 31kHz Cyclic ADC which based on the design index has been researched and implemented on this paper.In order to reduce the area and power consumption of ADC,system design adopted operational amplifier sharing technology to reduce the use of capacitance and operational amplifier.The Cyclic ADC designed and implemented on this paper was based on SMIC foundry CMOS process.After circuit and layout design have been completed,the proposed ADC has been simulated on the condition of a 3.3-V suppy and 31kHz sampling rate,the post simulation results showed that the ADC achieved an ENOB of 11.9 bit,a SNR of 72.14dB,a SFDR and SNDR achieved 85.86 dB and 71.76 respectively.The area and power consumption have reached the design index of ADC that the layout area of ADC was 119um×75um and ADC power assumption achieved O.11mW.