Design Of A Low Power Cyclic ADC For Pixel Cells

Because of the high frequency and short wavelength of X-ray,X-ray detector has been developed rapidly in recent years.X-ray detectors are widely used in medical,aviation and industrial fields because of their characteristics.The readout circuit of the lattice plane in the X-ray detector amplifies the detection signal,then de-noising a series of processing,and then ADC carries out analog-to-digital conversion.The output digital code will be processed by the subsequent digital signal processing module.For the readout circuit of pixel array,each pixel unit has a corresponding pixel level ADC for analog-to-digital conversion.As the interface between readout circuit and digital circuit,the internal module of pixel unit,area,power consumption and working frequency are the design difficulties of ADC.For the pixel array in the readout circuit of X-ray detector,the ADC area and power consumption in the pixel array are required.In this paper,by comparing the advantages and disadvantages of several common pixel level ADCs and analyzing the ideal model of traditional cyclic ADC,it is determined that cyclic ADC meets the system requirements of pixel unit.With the help of Simulink,the signal building error,thermal noise and capacitance mismatch are added into the ideal model to analyze the influence of each error source on the performance of cyclic analog-to-digital converter.The cyclic ADC can meet the requirements of ADC area and power consumption for pixel unit under the appropriate interference of error source.A low-power cyclic ADC applied in pixel unit of X-ray detector readout circuit is designed.In the bottom module design,ADC sampling circuit and MDAC sampling circuit share one op amp to realize the sharing technology of op amp.According to the principle that the DC gain and unit gain bandwidth of the operational amplifier in pipelined ADC decrease step by step,an adaptive bias circuit is designed to reduce the tail current of the operational amplifier in different cycles,which further reduces the overall power consumption of ADC.Reasonable timing and redundant bit algorithm can improve the tolerance of offset voltage and reduce the influence of kickback noise.With Candence platform and CMOS technology of SMIC,the circuit of 12-bit 100 k Hz Cyclic ADC are completed.The function and performance of the designed Cyclic ADC were verified.Results display that the SNR of 69.5d B,the SNDR of 68.5d B,the SFDR of 75.1d B,the THD of-75.4d B,and the ENOB is 11.09 bits.The overall power consumption of the ADC is 112?W and the area of the map in the pixel cell is approximately 130?m by 90?m,which meets the design targets of the system.