All-Region Noise Models For Mosfets And Their Applications In Low-Noise Operational Amplifier Design

As an important circuit cell in analog integrated circuits, CMOS operational amplifiers (opamp) have been used in more and more practical applications, such as automotive electronics, communication, consumer electronics, and military system etc. With the continual improvement of deep-submicron CMOS technologies, low voltage CMOS operational amplifiers are paid more attention than ever in analog integrated circuits. However, the decreasing power supply voltage will degrade the signal-to-noise ratio of circuits, which means that it is indispensable to improve the noise performance of circuits. MOSFETs are the dominant noise sources in CMOS operational amplifiers. Therefore, it is becoming an important issue for studying the noise models of MOSFETs and the design procedure of CMOS low noise operational amplifiers.Several problems have to be considered with CMOS technologies marching into deep-submicron era for improving speed and area etc. Firstly, the noise theory of operational amplifiers depends on the noise models of MOSFETs. Unfortunately, typical long channel noise models can not well predict the noise behavior of short channel MOSFETs, hence can not well predict the noise behavior of operational amplifiers. Secondly, with the power supply voltage decreasing, MOSFETs often operate under weak inversion or moderate inversion, which requires that the validity of typical noise models should be extended from weak inversion to strong inversion. Finally, the compromises between specifications become more evident with the power supply voltage decreasing, which means we should consider how to manually calculate the design parameters before simulation for coherent and timely circuit design.Aiming at the present problems, the all-region noise models valid for deep-submicron MOSFETs, the design procedure for CMOS low noise operational amplifiers, and the design and the noise analysis of high performance low noise operational amplifiers were studied in this paper. The study includes in detail as following aspects:Firstly, the all-region (from weak inversion to strong inversion, and from linear region to saturated region) noise models valid for deep-submicron MOSFETs were proposed using the generalized noise calculation methodology based on the physical mechanism of noise. The physics-based expressions for thermal and flicker noise, and flicker noise corner frequency constitute compact channel noise models. The noise models comprehensively considered the short channel effects. The carrier heating, channel length modulation, and mobility degradation due to the vertical and lateral electric field have been incorporated in the proposed thermal model. And the effect of the mobility and carrier number fluctuations on the flicker noise as well as the dependency of the mobility limited by Coulomb scattering on the inversion carrier density have been considered in the proposed flicker noise model. The measured results validate the proposed models.Based on the proposed all-region noise models for deep-submicron MOSFETs, as an example using a three-stage operational amplifier, a noise-oriented design procedure for CMOS low noise operational amplifiers was proposed. In the design procedure, we calculated the design parameters of the three-stage operational amplifier starting from the expected specifications, using the proposed all-region deep-submicron thermal noise model and the typical long-channel thermal noise model, separately. The results show that the calculated results using the former are closer to the simulated results by HSPICE than the latter. And, the measured results also agree well with the expected specifications. These results show the proposed design procedure can effectively guide the simulated design of operational amplifiers, hence improve the design efficiency. Based on the operational amplifier design, the equivalent input noise spectrum density was calculated from the proposed all-region deep-submicron thermal noise model. The calculated results are closer to the measured result than the simulated results by HSPICE. It shows the proposed noise models can well predict the noise behavior of operational amplifiers, and provide the theoretical foundation for the validity and accuracy of the proposed design procedure.Finally, three low noise operational amplifiers were proposed based on the proposed all-region deep-submicron noise models and the noise-oriented design procedure for low noise operational amplifiers: 1) A low noise operational amplifier design using V-NPN transistors. In this design, V-NPN transistors were used instead of typical MOS transistors as input differential pair for improving the noise performance. And a base-current compensation circuit was proposed for improving the larger base currents of V-NPN transistors. 2) A low noise operational amplifier design using DTMOS transistors. In this design, DTMOS transistors were used instead of typical MOS transistors as input differential pair for improving the noise performance. And combined cascade transistors were used for improving the lower output impedance of DTMOS transistors, hence increasing the gain of the operational amplifier. 3) A low noise constant transconductance operational amplifier design with rail-to-rail input range. In this design, the same-channel DTMOS transistors were used instead of typical MOS transistors as input differential pair for obtaining rail-to-rail input-common range and low noise performance. And a current adjustor was proposed for the constant transconductance in the whole rail-to-rail input range.The proposed all-region noise models for deep-submicron MOSFETs and the design procedure for low noise operational amplifiers were further verified using the aforementioned three low noise operational amplifiers. For verifying the proposed noise models, the equivalent input noise spectrum densities of the operational amplifiers using V-NPN and DTMOS transistors as input differential pair were calculated using the proposed noise model. The calculated results of the former are very close to the simulated results by HSPICE, and the calculated results of the latter like those in Chapter 4 are slightly higher than the simulated results by HSPICE (the calculated results are closer to the measured results than the simulated results in Chapter 4) . These results show that the proposed noise models can well predict the noise performance of the operational amplifiers. Furthermore, the design parameters (sizes and biasing) of the rail-to-rail operational amplifier were calculated using the proposed design procedure for CMOS low noise operational amplifiers. The calculated results are very close to the simulated results by HSPICE, which shows the proposed design procedure can effectively guide the design of circuits, and improve the design efficiency of circuits.