Investigation Of On-Chip ESD Protection For High-Voltage Process And Machine Model

In this dissertation, ESD protection strategies based on high-voltage self-protection, high-voltage outside-protection and Machine Model were investigated. Performances of ESD protection schemes are evaluated by Transmission-Line-Pulsing system (TLP) and semiconductor parameter tester. Some of novel and practical results are achieved. Related contents and conclusions as follows:1. A high-voltage self-protection strategie was proposed in0.35μm BCD high-voltage process. The ESD characteristics of large-array output driver nLDMOS was analyzed. Due to strong anti-ESD ability of reverse, it only needed to enhance the positive ability of parasitic transistor. However, the LDMOS-based driver circuits always show vulnerability to ESD stress (0.1mA/μm). This phenomenon is attributed to the inhomogeneous trigger sequence of the parasitic B JT and base push-out effect. NLDMOS using the extended-body technology was improved the self-protection ability.2. A high-voltage outside-protection strategie was proposed in0.35μm BCD high-voltage process. The study focused on the level and the factors that could affect the ESD protection nLDMOS features. Among them, the use of the RC detection circuit for gate-control nLDMOS could enhance the discharge ESD ability. And a distance of Lcont was the biggest impact factor of nLDMOS devices ESD characteristics. So reasonable control Lcont distance could greatly enhance discharging ESD capability of nLDMOS devices.3. ESD characteristics of the different structure types LDMOS-SCR devices were investigated in0.35μm BCD process. The study found that when the additional drain N+terminal was connected to a high-voltage node, the device will burn out at snapback as the first turn-on device is the parasitic NPN. Consequently it was noticed that we should design the N+implant near gate of layout. 4. Based on a0.35μm,30-V/5-V BCD process, some SCR-LDMOS ESD clamps with different drain floating N+regions were fabricated. We found that for device with such floating N+region make the current saturated at a high-current ESD discharge. This structure reduces the trigger voltage slightly while the breakdown voltage remains fairly unchanged. Simulation results indicate that the current saturation was due to the flowing of lateral drain current into the floating region and hence reduces the emitter injection efficiency of the parasitic BJT. Design optimization can be made by proper trimming the size and the location of the floating region which have been illustrated in this work by some TCAD simulations.5. Based on a0.35μm,30/5V BCD process, a novel waffle type LDMOS-SCR ESD clamp was fabricated. Compared to the traditional stripe type layout, the propose device structure shows a higher current limit of4.4A with a total layout width of60μm and an area of2323μm2. Considering the normalized failure current, the new layout structure increases the current capability by more than30%when compared with the conventional stripe structure. The high robustness, high breakdown voltage, and low leakage current characteristics, as well as the high area utilization efficiency, make the waffle layout structure be more attractive as a technological option for high-voltage ESD protection applications.6. Traditional cascade by increasing multiple to maintain voltage to reduce the risk of latch-up, however this would inevitably cause the weakness of increasement of the trigger voltage and on-resistance. Therefore low trigger voltage technology and low resistance technology was proposed. The trigger voltage of ZTSCR can reduce to about6V, and the conduction resistance of LRSCR can be reduced to half of the original.7. Based on a0.35μm,30-V/5-V BCD process, SCR-LDMOS stacking structure with proposed ring-resistance-triggered technique were fabricated. These devices were found to have better ESD robustness, high and tunable holding voltage in the proportion of the stacking unit number, properer trigger voltage and high portability. A comparison of the existing anode-cathode technique and merit of the proposed technique has also been presented to illustrate the meaning of the work.8. The relationship of Human Body Model and Machine Model was summarized. The ratio was10-12, however when the process line width below the deep sub-micron ratio was turned to15-20. Generally, the ratio of HBM and the MM level was generally rising in tandem style. Consequently MM-based should been protected by dual-direction SCR divices.9. The ESD protection characteristics of DDSCR were investigated in0.35μm CMOS low-voltage process and65nm CMOS low-voltage process. Due to two major drawbacks that too high trigger voltage and too slow open time of DDSCR, the DDSCR based on external trigger structure including MOS transistor, transistors, capacitors and diodes string was proposed. Moreover a novel Initial-On Pmos-Triggered DDSCR was proposed. Compared with traditional devices, the new proposed devices could have high robustness, low trigger voltage. And a full-chip ESD protection scheme was also proposed by the IPDDSCR.10. ESD detect clamping circuit was proposed by using the multiple current mirror. Compared to the traditional RC detect the clamp circuit, such circuit consumed a smaller layout area, and could reduce the cost of the chip.