Design And Implementation Of Multi-Rate LDPC Decoder Based On FPGA

The low-density parity-check code(LDPC)is adopted by most communication systems as a channel coding implementation because of its error correction performance and relatively low decoding delay.As the 3GPP organization determines the LDPC code as long code block coding scheme for 5G mobile broadband enhanced scene service data,the research on application of LDPC decoder has entered a new stage.With the increasingly wide application of LDPC code,single-rate decoder has been unable to meet the performance requirements of conventional communication systems.In order to achieve the optimization of overall performance,decoders of various rates compatibility need to be taken into consideration.Therefore,the study of high-speed,low-complexity multi-rate LDPC decoder and its concrete realization,is a key to push LDPC code into practical use.In this paper,the four-rate LDPC code with WiGig standard is used,the code length is 672,and the bit rate is 1/2,5/8,3/4,13/16.This paper mainly studies FPGA logic design and verification of multi-rate LDPC decoder,and the main work and innovation as follows:1,The influence of the correction factor and the maximum number of iterations on the decoder performance in the decoder design is analyzed,and the optimal parameters are selected by the experimental method.2.A comparison module based on bubbling structure can be used to match the comparison calculation of different degree distribution,and it can effectively reduce the occupation of hardware resources,which is the shortcomings of traditional first two minimum values comparison module.3,The sub-modules of the decoder are designed,which can match the decoding operation of multiple check matrix and a plurality of different check nodes,and the structure of the decoder is optimized Simultaneously,this paper completes the functional simulation of each sub-module and the whole decoder4,Based on the existing hardware environment of the laboratory,a complete hardware and software simulation and verification platform is built to complete the verification of the whole system.The verification results show that the design takes up less hardware resource consumption and has higher decoding throughput and higher practical value.