The Design And Implementation Of LDPC Encoding And Decoding Algorithms Based On FPGA

LDPC code is a type of linear block code with excellent performance, and it canoutperform the Turbo codes with sufficiently long block lengths. Compared with theunstructured random LDPC code, quasi cyclic LDPC code has a flexible construction andhigh realizablility, can be carried out in parallel design and realize module reuse, so it hasbecome to a research hotspot.Based on the LDPC theory, the paper presents a PS method to construct a specificparity-check matrix by building a shiftable matrix, which should match some definiteconditions. For (6075,5402) QC-LDPC code constructed by PS method, the performance of itwith different parameters are simulated based on the MATLAB software. Then the PSconstructed LDPC code and randomly constructed LDPC code with the same block length aresimulated and compared, and the results show that the method presented in the paper iseffective.According to the (6075,5402) QC-LDPC code, the paper gives the FPGAimplementation model, and designs the programs of the encoding and decoding algorithmsusing VHDL language under Quartus ΙΙ simulation platform. For encoding, due to the cycliccharacteristic of the generator matrix, the complexity of implementation is greatly reduced bythe feedback shift register design. For decoding, the minimal sum algorithm is simulated in apartial parallel structure. Then combined with Quartus ΙΙ and MATLAB software, thehardware simulation results are tested to make sure the correctness of hardware programming.Compared with the randomly constructed LDPC code with the same block lengths, theQC-LDPC code in the paper has the same excellent performance, but the difficulty andcomplexity of hardware implementation are much lower.