Rate-compatible QC-LDPC Encoder And Decoder Hardware Design And Implementation

In recent years, bacause of its high performance approximating the Shannon limit, low density parity check code(LDPC) has a broad application prospect. IEEE 802.11 n, IEEE802.16 e and DVB-S2 standards has adopted LDPC as their error control code, what's more802.11 ax adopts LDPC as its error control code. In order to satisfy the requirements of communication quality in different channels, it is necessary to do some research on multirate-compatible LDPC encoder and decoders.QC-LDPC is a kind of architecture-aware code that is generated by cyclic shifting the base matrix. With its quasi-cyclic feature, QC-LDPC code has much lower encoding complexity, which can make it easier to achieve parallel implementation and high throughput.First, based on SRAA and RLA algorithm, we propose a resource-saving encoder design aiming at the most widely used QC-LDPC code, which can be implemented on FPGA easily. Then we proved this method can be used for rate-compatible purpose.Second, from the perspective of decoder implementation, we compare 3 main streamed ways, including parallel, serial and serial-parallel methods, then we designed an LDPC decoder based on serial-parallel method.Finally, we give the simulation and synthesis results.The results show that our proposed method can keep the high performance of LDPC code as well as improving the efficiency of encoder and decoder from the aspect of throughput and resources.