Research And FPGA Implementation Of Multi-Rate Quasi-Cyclic LDPC Codes

The low density parity check(LDPC)code is a good code for error correction performance approaching the Shannon limit,and it is also one of the most attention-grabbing research hotspots in the field of channel coding.The quasi cyclic-LDPC(QC-LDPC)code is a kind of structural LDPC code obtained by cyclically shifting a basic matrix,which has the advantages of low implementation complexity and flexible construction of codewords,thus IEEE 802.11 n,5G(enhanced mobile broadband scene)and other communications standards employed it as channel coding schemes.With the popularity of the IEEE 802.11 n standard,designing and implementing a QC-LDPC encoder with a higher throughput rate is one of the directions for future development.In addition,with the wide application of 4G and the arrival of the new era of 5G,the user's demand for the transmission rate of the microwave communication system is increasing.Compared with improving the modulation order and bandwidth of the system,designing the error correction code with a higher code rate is the preferred method to promote data throughput in microwave communications systems.The paper focuses on the above two issues to study,the main tasks include:Firstly,we study the practical LDPC encoder of the IEEE 802.11 n standard.Considering the problems in the prior art is the high resource consumption of the full parallel encoder and low throughput of the serial encoder.To solve the problem,an improved dual parallel encoder is further studied and proposed.Compared with the serial encoder architecture,the improved encoder increases the data throughput rate by more than 20% on the premise of a small increase in resource consumption.Secondly,designing of high-rate QC-LDPC codes is studied.The demand rate of errorcorrecting code rate in microwave backhaul links is analyzed to determine that the designed QC-LDPC code rate is more than 0.92.Then three kinds of LDPC codes are analyzed.Based on the advantages and disadvantages of commonly used design methods,an LDPC code with a code rate of 0.921 was designed using an array QC-LDPC code construction method.Simulations show that the LDPC code designed this time has good BER characteristics.Finally,based on VHDL,the high rate QC-LDPC code is implemented in FPGA,and the simulation and synthesis are completed using Modelsim and Vivado software.The integrated results show that this FPGA implementation has low resource consumption and maximum support clock is 314.7MHz and the throughput rate is as high as 321.4Mbps.Then the KC705 development board was used to download and test the implementation.The results show that the implementation is functional and applicable in practical projects,and it meets the expected design requirements.