Multi-mode Concatenated ECC Research And High Speed Fpga Realization In DVB-S2 Standard

At present, the Forward Error Correction(FEC) code has been widely used in modern digital communication systems because of its remarkable ability to resist the impact caused by channel noise. Compared with the conventional single FEC code, a concatenated code can combine the advantages of both outer code and inner code to further reduce the error rate and to achieve the channel capacity. Therefore, many current communication standards adopt the concatenated code. For example, the Digital Video Broadcasting Satellite-2nd Generation(DVB-S2) has determined the BCH+LDPC(Bose Chaudhurl Hocquenghem and Low Density Parity Check Code) as its FEC code, for which the LDPC code possesses a BER performance achieving to the Shannon limit. In addition, several other communication systems have also adopted BCH+LDPC concatenated codes as their FEC, e.g. Digital Video Broadcasting-Terrestrial Second Generation(DVB-T2), Digital Video Broadcast-Next Generation Handheld(DVB-NGH) et al. In order to cater the different radio channel, most of the standards can enable multi-mode concatenated codes, such as 21 permitted modes in DVB-S2 standard.Considering the difficult hardware implementation resulting from the long codeword and various code-rates of BCH+LDPC code in DVB-S2 standard, this paper designed a high-speed LDPC decoder without any loss of decoding performance for its FPGA realization using the improved Min-Sum algorithm. A complete FPGA realization and simulations of BCH+LDPC concatenated code have been studied.Firstly, based on MATLAB, the Bit Error Rate(BER) performance of BCH code and LDPC code are simulated under the AWGN channel, respectively. Specially, the paper has compared the computation complexity and BER performance with different decoding algorithms of LDPC code. Simulations show that the proposed decoding algorithm can obtain about 0.1d B performance gain without any increase in its decoding complexity.Secondly, a FPGA-based LDPC decoder according to DVB-S2 standard is realized on Xilinx ML605 FPGA board. The synthesis results and simulations show that the proposed OMSA(Offset Min-Sum Algorithm) can not only reduce the LDPC decodingcomplexity, but also improve the BER performance by about 0.8d B, compared with the NMSA(Normalized Min-Sum Algorithm) under the AWGN channel. In addition, the system maximum throughput can reach 132 Mbps when the working clock is 100 MHz. Finally, the FPGA-based BCH+LDPC concatenated codes according to DVB-S2 standard has been realized and tested on ML605 development board. A BER performance under the AWGN channel of decoder with and without LDPC concatenation code has been compared. Analysis shows that LDPC appears the error floor when the BER varies from 10-6 to 10-12 for the 21 modes in DVB-S2, while with the proposed BCH+LDPC concatenation, the BER error floor can be remarkably dropped to less than 10-10.