Design Of A Low Power Digital Baseband Processor For UHF RFID Tag

The radio frequency identification?RFID?technology is a technology that the reader complete the target recognition through the contactless two-way data exchange by radio.The technology is rapidly being used in areas such as intelligent transportation,healthcare,retail logistics and security.In recent years due to the needs of technological development,UHF RFID technology in RFID technology has become a major research hotspot.Because the power supply of passive tags comes from the coupling of space electromagnetic field,the low power consumption design is the crucial factor that affects the performance of UHF RFID electronic tags.In the electronic tag chip,the digital baseband part of the total power consumption of more than 40%.For this problem,a UHF RFID digital baseband processor compatible with the EPC^TM C1 G2/ISO 18000-6C protocol was designed in this paper.This paper first introduces the background and significance of RFID technology research,as well as the development status and research focus.Then the whole system of UHF RFID was introduced,and the EPC^TM C1 G2 protocol was analyzed in detail.Including reader and tag communication specification and communication process,link time limit and instruction set.Through the relevant theoretical analysis,a baseband processor architecture based on the EPC^TM C1 G2 protocol and the corresponding sub-modules in the architecture were designed.The root factors affecting the power consumption of CMOS integrated circuits were analyzed.In view of these factors,this paper has completed some low-power design,such as clock domain design,pipelined architecture,asynchronous circuit design,gated dynamic management of clock signals,and operand isolation.Also,the purpose of reducing power consumption as much as possible was realized through these low-power technologiesAccording to the design flow,the RTL code was completed and passed the function simulation verification.At the same time,the logic synthesis was realized based on the SMIC0.18?m CMOS process using the Design Compiler tool of Synopsys company.And the generated gate level netlist passed the post-simulation verification.Then,the power consumption of the baseband processor was analyzed by PrimeTime,and the physical implementation process of the digital back-end was completed with the IC Compiler tool,and the layout was finally generated.The baseband processor's board level verification was passed that using the reader and FPGA to build the verification platform.When he design of the baseband processor in the SMIC 0.18um process and the use of1.8V operating voltage,the digital circuit layout area 561?m×215?m was achieved and the average power consumption was 8.23?W.Simulation and experimental results indicated that the work is normal and the desired goal of the design was achieve.