Research And Design Of The Baseband Processor For Uhf Rfid Tag

RFID (Radio Frequency Identification) technology is one of the contactless automatic identification technologies and uses radio frequency signal to capture information automatically, accurately and flexibly. A typical RFID system consists of reader, tag and application software. The RFID tag carries the ID data; the reader interrogates the tag and extracts the data from it; application software acts as an interface between the user and the RFID system. Now, RFID systems have infiltrated the market in uses for everyday life, such as access control, mass transit ticketing, supply chain management, health care and retail, etc. Realization in the business community of the benefits of widespread adoption is fostering explosive growth of radio frequency identification technology.This paper presents a baseband processor design of UHF RFID passive tag, which is compliant with the EPC Class1Generation2(ISO18000-6C) protocol. Firstly, development of RFID history, basic working principle and application prospects are introduced. After that, this paper discusses the EPC C1G2protocol in detail, including physical layer, command structure, communication process between reader and tag and so on.Complying with the requirements of protocol, the system architecture of digital baseband is proposed, and the design of the modules is finished, for example, PIE decoding module, CRC (cyclic-redundancy check) verifying and coding module, FMO and subcarrier Miller-modulated coding module, random number generator (RNG), clock management module, power management module, memory management module and control unit.Passive tags do not posses an on-board power supply in the form of a battery and rely only on the power emitted from the reader. Therefore, power dissipation is one of the important specifications for passive RFID tag. Obtained through the power consumption analysis of the tag baseband, dynamic power occupies most of the total power consumption, so several low power techniques are employed to reduce the power consumption of the baseband including2.56MHz&1.28MHz dual-clock strategy, clock gating, the unit switching function and asynchronous counter. These methods effectively reduce the power consumption of the baseband.Reference to the ASIC design flow, the digital baseband processor has been described in Verilog HDL language at RTL level and verified by the Xilinx FPGA platform, which ensures the correctness of system functions, as well as the RTL code can be integrated, then, the design is implemented with Synopsys Design Compiler tools for synthesizing. After that, this paper completes the power consumption analysis of the gate-level netlist circuit and the design of layout with Cadence SOC encounter for placing and routing.The baseband circuit is implemented in TSMC0.18um CMOS process. The power consumption is6.4μ W under1.8V supply voltage. The layout area is407μ m×391.5μ m. The test results indicate that the design of UHF RFID passive tag baseband processor is reliable and conforms to EPC C1G2protocol and the prospective task.