| Radio Frequency Identification(RFID),which identifies target tags using RF signal without contact, is widely adopted in industries sucn as logistics tracking, personal identification, anti-fake and so on. Ultra High Frequency(UHF) RFID has provides wide communication range, high data rate and low-cost Tags, which has grown considerately in the last years. It is estimated that the UHF RFID will become the main RFID market in 2017. Power consumption of the passive UHF RFID tag limits the communication range, it is crucial to design ultra-low power circuits for passive transponder to guarantee a longer communication distance performance. Thus this thesis focus on the Tags low power baseband Processor design。Firstly, the thesis descirbes the basic knowledge of CMOS power comsumption. Considered with the Tag architecture and EPC Class-1 Generation2 protocal, some special power requriments in UHF RFID Tag are discussed. Then the thesis reviews the common low power design methods.Secondly, a novel low-power digital baseband controller architecture is presented. The thesis analyzes baseband datapath and each sub module functions including protocol requirement, implementation and simulation result. Compared to other design, asynchronous technique and three-level clock gating technique are adopted to manage the Tag work timing. From top module to gate level, at the best efforts to reduce cell redundancy activities to save power. Based on the timing structure, The baseband use the share technique, asynchronous counter, reducing sub module clock frequency, one-hot encorder for counter and double-edge design to lower the power consumption. Test results show the processor consumes is less than 6.24μW at 1.8V supply voltage and the three-level clock gating brings more than 50% power consumption reducing.Thirdly, the design accomplisies logic synthesize and physical implementation by Synopsys EDA tools(Design compiler,IC compiler,Primetime). Back-end flow procedures and low power constraints writing are elaborated. The result satisfies timing closure and physical verification.Finally, the design downloads the RTL code to do the FPGA verification and tape out in SMIC 0.18μm CMOS technology. Measurement results show the baseband is in full compliance with the protocol, the Tag’s sensitivity is-14.5dB m. |
