Design And Implementation Of Low Power For Digital Baseband Processor Of RFID Tag

Radio frequency identification (RFID) technology provides a method to capture information automatically, accurately and flexibly. With the development of information technology, the applications of RFID increase rapidly and widely. RFID will become one of the fundamental technology in the future information society. However, the development of RFID is restricted to the power consumption. It is more and more important to research the low power design for RFID to meet the market requirement of low cost, the performance requirement of long operation range and high data rate and so on.The fundamental theory and structure of RFID technology are discussed in this dissertation. The technology of low power design are analyzed and platforms for simulation, verification and evaluation of power consumption were implemented, which make sure the low power design for SIM card chip works effectively. How to design a low cost low power RFID tag chip for its digital baseband processor is studied and the solutions are given.Firstly, the principle,the structure and the module of RFID are investigated in detail and RFID is classified by different characters. In addition, the standard of RFID, one of factors which have effect on the development of RFID technology, is introduced.Secondly, in order to get low cost and high performance chip, the analyses of varieties and sources of power consumption of CMOS circuit are studied and platforms for evaluation of power consumption in different design level are analyzed, which are the theory foundation and reference for low power design. A simple digital baseband processor is designed based on ISO/IEC18000-6 protocol. Therefore,the tag prototype is designed, optimized and implemented according to the requirement of modules.Finally, the solutions of the low power design for RFID digital baseband processor are proposed. Dynamic Power Management is used for the whole system. The operands isolation in MUL module, pipeline structure, clock gating and state-machine encoding were implemented in logic level. The simulation and test result by Power Compiler software proved that the requirement of low power is satisfied.