The Low-power Chip Technology And Its Rfid Applications

With the rapid development and broad application of VLSI technology, the dissipation of power, which causes many problems, such as energy dissipation, package cost, heat with high density and so on, attracts more and more attention. Nowadays, low-power technology is the key point and hot spot for VLSI research. Currently, the low-power technology is involved in three areas: process, package and circuit design. Compared to others, the circuit design features lower cost, broader application and greater space for optimization. Therefore, this paper makes a deep research on the low-power technology for the circuit design, and applies it into a typical low-power wireless communication system - RFID (Radio Frequency Identification).Firstly, this paper analyzes the characters of low-power requirements in different power-supply systems and distinguishes the conceptions between "low energy" and "low power". And based on the operation theory of the RFID tag, a distributed architecture for baseband-processor is proposed which meets the special requirement of the RFID tag.Secondly, four basic methods for power saving and kinds of low-power techniques adopted at the design phases, from system-level to transistor-level, are presented. These techniques are applied into the RFID tag design. Meanwhile, a novel scheme for generating pseudo-random numbers and a new partial decoder circuit are proposed. The baseband-processors for the UHF, HF and LF tag are designed and implementated separately. The experimented results show that our design achieves the expected objective and possesses high performance on power saving compared with the foreign counterparts.Thirdly, a deep research is made on a novel low-power technology -- adiabatic circuit technology. A new quasi-static adiabatic logic is proposed, which can efficiently avoid the power caused by redundant charging/discharging for the circuit nodes. And based on it, an adiabatic latch with set/reset function is presented to complement the logic function for the adiabatic logic family. Besides, an adiabatic ROM cell is proposed by applying the adiabatic circuit technique into the ROM, which can reduce amounts of dynamic power caused by charging/discharging the load capacitances of the bit lines when accessing the ROM. Meanwhile, in order to improve the application of adiabatic circuit technology, a semi-automatic design strategy for the adiabatic circuit is presented and the related adiabatic standard cell library is also built up. Finally, these research fruits are applied into the RFID system and an adiabatic LF tag is developed and now the chip is under testing.The simulation results show that the adiabatic baseband-processor can achieve about 88% power saving compared to the conventional CMOS counterpart.