Research And Application Of CMOS Broadband VCO

Integrated circuits are the cornerstone of information society.Phase-Locked Loop Frequency Synthesizer?PLLFS?with Voltage-Controlled Oscillator?VCO?are the heart of the wireless communication,and many of their indicators affect the performance of wireless communication systems.With the improvement of microelectronics and the development of wireless communication technology,the design of silicon based CMOS process RF integrated circuit?RFIC?has become a hot topic of academic research.In this thesis,the basic principle,common structure and design methods of VCO and PLLFS are studied.An X-band wideband linearly-tunable LC-VCO is designed based on HHGRACE 0.13?m CMOS process.The specific application of LC-VCO is studied,and a fractional-N PLLFS with Auto Frequency Calibration system?AFC?is designed.The research work is summarized as follows.Firstly,this thesis investigated the recent research of X-band VCO and PLLFS,analyzed the basic principles and circuit structure of VCO and PLLFS,and studied simulations,designs and implementations of a digital and analog hybrid chip.Secondly,the design of broadband,linear tuning,low phase noise and low power of X band LC-VCO is studied.The switched capacitor of digital signal control is used to achieve broadband design.The C-V tuning characteristic of varactors is used to optimize the design scheme,which improves the VCO tuning linearity.The phase noise performance are improved by negative resistance structure and high Q value of passive devices,and low power design is implemented by using current reuse technology and low supply voltage.The circuit design,physical design,rule checking and post simulation of X-band wideband linearly-tunable LC-VCO is completed.The post simulation shows that the output frequency range covers 9.678-10.976 GHz,tuning bandwidth is 12.57%,and?35?K_VCOis 29.76%.The phase noise is-110.43 dBc/Hz when output frequency is 9.75GHz at 1 MHz frequency offset and the phase noise is-107.14 dBc/Hz when output frequency is 10.6 GHz at 1 MHz frequency offset.The power consumption is 4.2 mW,and the expansion performance factor is-183.40 d Bc/Hz.Thirdly,the design of a X-band Fractional-N PLLFS,including prescaler circuit,differential to single terminal circuit,programmable multi-mode divider?PMMD?,?50??35?modulator,phase and frequency detector?PFD?,charge pump?CP?and AFC circuit.The PMMD is designed to achieve any integer frequency division of 64-127,the?50??35?modulator uses 24 bits MASH structure digital modulator,and SPI slave interface is integrated to reduce the number of chip pad.A full digital AFC module with two-points search algorithm is designed.The simulation results show that the longest calibration time of the AFC circuit is about 20?s.The ultimate realization of the PLLFS from behavioral simulation,circuits design?gate level circuit?,EDA simulation,physical implementation of whole process,and the finally area of chip is 0.980?0.830 mm².The simulation results show that the locking time of Fraction-N PLLFS is less than 10?s,and the power consumption is 42 mW.The design of PLLFS chip was taped out under HHGRACE 0.13?m CMOS process.Fourthly,the chip test work of LC-VCO and PLLFS is completed.The test scheme is formulated,the test circuit is designed,the chip COB package is completed,and the test results of this design are analyzed.