The Design And Implementation Of A Phase-locked Loop With Fractional-N Function

Phase-locked loop is widely used in electronic system.With the rapid development of modern communication technology,higher requirements are proposed for phase-locked loop circuit.In many applications,the phase-locked loop has a high frequency resolution.When the frequency resolution is increased,the division ratio between the output frequency and the input frequency will increase and Phase noise will also increase.In order to achieve small noise and high frequency resolution,the fraction-N technology is needed.In order to save the time of research and development in the later application with wide application of phase-locked loop,the circuit and layout need to have a certain process compatibility,design redundancy and modular design.In this thesis,take the design and implementation of a phase-locked loop with fractional-n function as the research object.The circuit design of phase-locked loop is discussed.Then the layout design and chip test are described.The main contents are:1.The analog circuit design of PLL is discussed.According to the basic structure of PLL is proposed to design the circuit and described the design of every module.This circuit design has design redundancy and according to the electrical design rules of major main foundries,some minimum dimensions of the device are stipulated.So this circuit can tape out in different feature sizes.2.This paper discusses the design of digital fraction-N divider.Using the fraction-N division technique,a higher frequency resolution can be achieved with a smaller frequency division ratio.Using the Sigma-Delta algorithm can reduce the noise of the system.3.Introduce the layout design of phase-locked loop.According to the requirements of the circuit design,complete the layout design and the testchip design.Each function module of the layout is designed by modularization,which facilitates the increase or decrease of the circuit function.According to the design rules of the major foundries,the minimum size of the graphics is limited.So this layout can tape out in different foundries.4.The test method and test result of the testchip are discussed.A variety of tests,such as power test,voltage combination test,multi chip test,clock jitter test,high and low temperature test and frequency lock range test,are carried out on the testchip.The quantitative analysis of the test results provides a reference for the improvement of the circuit and layout.The test results of 180 nm testchip and 160 nm testchip which under the same circuit prove that the PLL circuit has design redundancy and process compatibility.