Design Of Low-power SAR ADC And Fully Integrated RSSI Based On 5.8GHz DSRC ETC Transceiver

The Electronic Toll Collection system?ETC?is typical application of Internet of Things?IoT?technology.IoT demands low cost,small form factor,low power,good reliability and high energy efficiency.To meet these rigid design requirements at the same time,the best design option is fully-integrated SoC that integrates RF,analog and digital circuits as a complex single-chip digital communication system.Based on these theorys of communication principle and analog integrated circuit design,etc.this thesis studied in details of the successive approximation register?SAR?ADC and received signal strength indicator?RSSI?,which are key front-end blocks in a RF receiver for a 5.8 GHz DSRC ETC.The demand for power consumption of ADC is the most serious in this 5.8G DSRC ETC fully integrated chip,the demands for speed and accuracy are not particularly severe.By comparing the performance of several mainstream ADCs,we find that the SAR ADC consumes the lowest power at the same sampling rate and accuracy requirement,the SAR ADC meets the requirements of the fully integrated chip.There are two kinds of applications for SAR ADC,one is that working as main ADC converts the IF signal into digital signal in the receiver link;another is as an auxiliary ADC with the RSSI circuit to detect receiver signal strength on the link to provide the basis for an automatic gain control algorithm.An 8bit 32.768MHz SAR ADC is implemented in SMIC 0.13,it adopts a variety of design methods to optimize area,power,and speed.The digital-to-analog converter?DAC?employs split capacitor array structure and“V_CM-based”switching to cut down the total capacitance,as well as power consumption.In sampling phase,the up and bottom plates of capacitor adopted bootstrapped switch circuit to avoid the introduction of non-linearity by switch;a double tail dynamic latch comparator was proposed without static power.The ADC used asynchronous logic control to optimize sampling rate.Based on 1.5V power supply and32.768MHz clock frequency,simulated results indicated that it achieved a SNDR 47.633dB,which effectively reached 7.62bit,while dissipating 0.516 and resulting in a figure of merit?FOM?of 80fJ/Conv.Compared with the traditional SAR ADC,the ADC meets the low-power design requirements and enhances its overall performance.In this paper,a novel RSSI circuit and architecture are proposed and implemented for5.8GHz DSRC ETC system.Two RSSIs collaborate with auxiliary ADC circuits to provide the digitalized received signal strength to the digital baseband of a transceiver in this system.Internal active LPFs in the DCOC loop enables fully on-chip integration of RSSI circuit,which effectively leads to fast transient response.In order to meet the requirement of the wide input range,two RSSIs with a smaller dynamic range are used instead of one RSSI with a larger dynamic range.Thus,the design complexity of the RSSI circuit is alleviated.Chip measurement results show the overall input dynamic range is 86d B,the accuracy is±1.72dB,and the transient response is less than 2?s.Compared with the state-of-the-art designs in the literature,the overall input range and transient settling time are improved by at least 14.6%,and 300%,respectively.In summary,this article describes the design of the SAR ADC and RSSI used in the RF receiver for the 5.8GHz DSRC ETC system and the implementation of the AGC algorithm.The specific module design and pre-simulation results of these two circuits are given respectively in the paper.Since the chip has no fixed pins for testing SAR ADC and RSSI separately,we test their overall performance.During chip testing,we determined that the design of the SAR ADC and RSSI met the design requirements of the system and was working properly.