Research And Design Of Fast Transient Response No Chip Capacitor LDO

All kinds of electronic products have been integrated into people’s daily lives along with the rapiddly development of intelligent terminal equipment,such as phone, bracelet, watch, television as well as the increasingly popular smart home. Integrated Circuit as a core component of electronic products, not only makes the product volume decreases, but also reduce the costs, reduce power consumption and meet the international situation--low-carbon environment.A capacitor-less LDO structure is proposed in this paper, the characteristics of transient and stability taked a major concer. Error amplifier, regulator, slew-rate enhancement circuit are optimizated and designed, respectively. As a result, the new structure achieved a higher stability and reduced the risk of chip failure or logic chaos.The method to improve the transient response is researched in this paper. The characteristics of transient response is enhanced by use an appropriate structure after studying several types of error amplifier.With the researching of the regulator,a parameter optimization method is proposed through theoretical derivation.The transient response of the capacitor-less LDO have been researched.First, the chip-off capacitive function of traditional LDO is studded,and then focus on the transient characteristics with the theoretical basis of the capacitor-less LDO researched before. A slew-rate enhancement circuit is proposed according to the factors which effect the transient characteristics. During transient,the proposed circuit detects output-voltage changes,then converted to a current signal feed-back to the OTA.The output voltage overshoot is reduced by the slew-rate of the regulator increase.The loop stability of the capacitor-less LDO has been researched. Detail calculation and derivation for the Small-Signal of the capacitor-less LDO,the loop is stabilitied with the RC compensation circuit which form a left-half plane zero after the dominant pole, phase margin is enough independent of the load changes.At last, transient-enhanced capacitor-less LDO voltage regulator was designed in the 0.5μm standard BICMOS technology with improved and optimized the transient response characteristics. By simulation,this circuit proposed in this paper with improved fast transient response and high open loop gian and wide band width(BW), the input voltage range is 2.8～5.0V, the output voltage is 2.4V. The characteristic of direct current、alternating current、 transient and temperature simulation and verification by Hspice.The maximum voltage step is about 159mV at a load step of 100mA/1μs under typical craft condition. The voltage differential is just about 16.8mV in the heavy load and light load respectively. The maximum voltage step is about 174mV in the two extreme case. The 3dB band width is 1668Hz and the OdB band width is 30.7megHz for the whole chip compensation capacitor just of 4pF, and without output capacitor.