A Chip-area-efficient Capacitor-less LDO Regulator With Fast Transient Response

The rapid development of portable electronic products has made power management chips play an increasingly important role in the current electronics industry.In this scenario,low-dropout(LDO)voltage regulators have turned into the preferred choice for low-voltage on-chip power management solutions,because of their fast response,simplicity and low cost of implementation.This thesis mainly studies and designs a capacitor-less low-dropout linear regulator with high area efficiency and fast response.The first chapter of the thesis gives a brief introduction and analysis of the system composition of LDO;In the second chapter,the basic principles of LDO and the definition of various performance specifications are elaborated,and the research trends of LDO in recent years are briefly analyzed and summarized.The third chapter introduces and analyzes the design method of conventional fully integrated LDO,and proposed a new frequency compensation method for the drawbacks of traditional LDO design.The method reduces the value of the compensation capacitor in the traditional design while ensuring the stability of the circuit,thereby achieving high chip-area efficiency and improving the response speed of the system.On this basis,the fourth chapter mainly optimizes and improves the design limitations of the proposed method.To better suppress the overshoot/undershoot of the output voltage due to load current stepping within a small time,adaptive biasing and dynamic slew rate enhancement techniques are employed.Consequently,the transient response speed of the LDO is further improved as the design requirements are met.The simulation results show that under the same simulation conditions,the response speed of the LDO designed by this method is better than the traditional LDO design.Finally,the fifth chapter of this thesis presents the test results of the proposed LDO to verify its performance and whether the specifications meet the expected design requirements.The design is performed by using the TSMC 0.18?m process.The chip area is0.0096mm~2.The regulator provides a maximum output current of 30mA for up to110pF capacitive load.The test results showed that the performance of the proposed LDO regulator is set to the given specifications and improves some qualities of conventional design,such as fast transient response,small chip area and high stability.When the load current steps from 1mA to 100mA within 400ns,the overshoot and undershoot of output voltage are 19mV and 35mV,respectively.