Design And Verification Of Physical Coding Subplayer Main Modules Of RapidIO

In recent years,with the rapid development of communication technology,the increasing processor frequency on the embedded system bus frequency and bit width put forward more stringent requirements.Rapid IO is the only open interconnection standard,with low latency,low pin count and high reliability and other features.Based on the "XX high speed serial Rapid IO switch chip",this paper focuses on the physical coding sublayer of Rapid IO2.2 protocol and participates in RTL code design and function verification of key modules.The main work of this paper is as follows:1)After studying the Rapid IO2.2 protocol,this paper first clarifies the interface design and design of the key coding of the physical coding sublayer,and then designs the architecture of the physical coding sublayer.On this basis,the completion of the transmission bit width conversion,8B / 10 B codec,flip control,channel synchronization and alignment operations.Which as the difficulties of the design of channel synchronization and alignment module,including Comma detection and synchronization,receive synchronization cache,receive alignment,channel binding and receive elastic cache five sub-modules.The main completion of the data Comma detection and synchronization,binding alignment and solve the problem of recovery clock and local clock does not match.2)In order to ensure the reliability of data codec in the channel,this paper designs a built-in detection circuit PRBS generation and detection module and introduces the design and verification process in detail.The PRBS supports both 16-bit and 20-bit modes to test the 8B / 10 B codec and serial-to-parallel converters Ser Des channels to ensure that the data is encoded to the correctness after being decoded.3)According to the overall design architecture of the key blocks of the physical coding sublayer,the PRBS detection circuit in the PCS layer first verifies the circuit from the coding module to the decoding module.And then put forward the Xilinx SRIO-based test platform,completed the entire path of the PCS simulation and verification of key points according to the preparation of targeted test cases through the test,based on the statistics of the function and code coverage.The simulation results show that the function of each module is correct.The physical coding sublayer designed in this paper realizes the expected function and conforms to the design index.