Physical Coding Sublayer Design Based On PCIe4.0 Protocol

High-speed serial bus(Peripheral Component Interconnect Express,PCIe),as the most popular of I/O universal bus in current market,has developed rapidly since it was announced by the Peripheral Component Interconnect Special Interest Group(PCISIG)in 2001 with its low-cost and high-speed advantages.It is gradually replacing the rest of the buses as an industry standard bus,therefore,it has certain market value and significance for the study of PCS layer circuits that meet the requirements of PCIe 4.0protocol.Based on a comprehensive study of the PCIe 4.0 official protocol,this thesis reviews a large number of relevant literature,analyse the architecture and topology of PCIe in detail,and focuses on the hierarchy of the physical layer.PCIe has a total of three layers,with the physical layer asthe bottom layer,which can be further subdivided into a Physical Code Sub-layer(PCS)and a Phycial Media Attachment(PMA).The PCS layer is mainly responsible for the encoding and decoding of data,which is a pure digital logic circuit and has an important position in the physical layer.This article refers to the Physical Interface for PCI Express(PIPE)to design a PCS layer circuit that meets the requirements of the PCIe 4.0 protocol.According to the direction of data transmission,the PCS layer design module includes two parts in the logic function,sending and receiving,and the transmitting part mainly includes input signal synchronization,input bit width conversion,8b/10 b coding,and 128b/130 b coding.The receiving part contains data boundary alignment,elastic buffer,8b/10 b decoding,128b/130 b decoding,output bit width conversion,and output signal synchronization.After the design code is completed,use Lint for syntax and structure checking,use CDC tool 0in to do cross-clock domain check,and after the code is correct,do VCS software simulation.Software simulation uses Verdi and VCS to do joint simulation to ensure the correctness of the function.After the functional verification,the DC synthesis tool is used,and the SMIC 28 nm CMOS process is adopted,and the operating frequency is 500 MHz,and the timing,area,and power consumption indicators after synthesis are ideal to meet the requirements of PCIe 4.0 protocol.