Font Size: a A A

Design And Implementation Of The Physical Coding Sublayer Unit Of FT-XDSP Gigabit Ethernet Controller

Posted on:2016-10-20Degree:MasterType:Thesis
Country:ChinaCandidate:J L YangFull Text:PDF
GTID:2348330509960525Subject:Software engineering
Abstract/Summary:PDF Full Text Request
In the current society, electronic equipment is increasingly networked. More and more electronic devices are required to have the network function. Ethernet becomes the first choice for many embedded devices, because of the advantages of simple struction, flexible, easy expansion, high reliability, low cost, abundant software and hardware resources.Based on the independent research and development of multi-core FT-XDSP by National University of Defense Technology, the paper aims at designing and developping the physical coding sublayer unit of multi-core FT-XDSP MAC module. We hope it can be correctly integrated into FT-XDSP, and achieve the expectant function. Based on the functional requirement of the physical coding sublayer unit, this paper deep studied the protocol of the Ethernet architecture, finally has done the following work for the implementation of the physical coding sublayer unit.1. Based on deep understanding the function requirement of the physical coding sublayer, this paper achieved the overall framework design. We divided PCS unit into transmitter, receiver, conflict detection unit, carrier detection unit, 8B/10 B encoder, auto negotiation unit, 8B/10 B decoder and synchron detection unit by adopting the top-down chip design thought.2. Based on the realization principle and realization process of every unit, we used the Verilog hardware description language to describe the function.3. We built the module level and system level verification platform and made the verification plan. The paper detailedly verificated the physical coding sublayer unit from the module level to the system level. At last, verification result showed that the function of physical coding sublayer was correct, and it could correctly work in the MAC controller.4. In the 40 nm CMOS technology, we used the DC tool to synthesize the physical coding sublayer unit. The result showed that the area was 3409.224, the power was 0.2251 mw. At last, the frequency could be up to 500 MHz.
Keywords/Search Tags:Ethernet, physical coding sublayer, 8B/10B, auto negotiation, synchronous detection
PDF Full Text Request
Related items