Research And Implementation Of Highspeed Transport Network’s Physical Coding Sublayer

Nowadays, with the rapid progress in information technology, people desire a wider and faster broadband. This demand takes the traditional communication pipe big pressure. As the 100 G transport network’s generalization in worldwide, people start to consider the next generation transport network. Meanwhile, the standards-setting organizations start to draft relevant standards. People can foresee that in the near future, highspeed transport network will play an important role in global communication network.The main content of this dissertation is the logic implementation of PCS(Physical Coding Sublayer), which is based on the FPGA(Field Program Gate Array) platform. The whole design references the IEEE 802.3ba standard and relevant drafts. In the foundation of highspeed transport network’s technical background and hierarchy structure, the dissertation makes a detailed description in PCS coding principle and key technology: with the analysis of scramble register, we realize the synchronization scramble arithmetic; with the design of flow adapter, we make the transport network more efficient and intelligent; with the design of synchronize marker and alignment marker, we ensure the network align and repair automatically; with the design of block-strip and bit multiplex, we finish the adapter after multiple lane distribution; with the design of CRC(Cyclic Redundancy Check), we guarantee the data be received exactly.The logic design is based on the MLD(Multi Lane Distribution) mechanism. MLD is the core mechanism of this dissertation. In PCS, the data is distributed into multiple virtual logic lanes. We call these lanes virtual lanes. Then in these virtual lanes the data is processed individually. In this dissertation, the highspeed data stream is distributed into multiple low speed lanes. Each lane is processed individually. When it’s needed we merge the multiple low speed lanes into highspeed lanes. With this method, we resolve the problem which we can’t adapt to the highspeed physical channel and optical wave directly.At last we finish the verification and simulation of this logic design. For each module, the dissertation provides the simulation wave and the verification wave through the integration of up and down stream, and compares the input data and output data. In the process, the simulations are based on modelsim from Mentor company; the hardware implementation is based on the vivado develop platform from XILINX company, with this support we finish the synthesization, implementation, place and route and debug; the hardware uses the Virtex-7 series XC7VX980 T chip, the design language uses verilog.