Resarch And Implementation Of Key Technologies In Wireline Transmission Link For 100g/400 GbE

As the new Internet services such as big data centers,8K/4K high-definition video,augmented reality/virtual reality(AR/VR),Internet of Things(Io T),and 5G cloud services,are being rapidly developed,the bandwidth demand of network communication data are getting higher and higher,which directly promotes the evolution of Ethernet data rate from 40Gb/s,100Gb/s to 400Gb/s,or even 1Tb/s.The 100G Ethernet standard IEE E802.3ba was promulgated in 2010.In Dece mber 2017,the 400G Ethernet standard IEEE802.3bs was also passed,which marks that Ethernet moves toward higher speed.However,while the transmission speed is continuously increasing,the signal integrity of wireline transmission link is also facing more challenges,which poses higher requirements about the link model,equalization,error correction and interleaving,the design and imple mentation of key chips.Though modeling and simulat ion,theoretical derivation,and circuit design and imple mentation,this dissertation makes deeply research on the key technologies of wire line transmission link in 400GbE,which promotes the research,development and application of high-speed communication systems,communication chips and related fields.In this dissertation,the IEEE802.3bj and IEEE802.3bs standards for 100/400G Ethernet are briefly introduced.And then the dissertation starts with the physical layer architecture and focuses on the main functions and working principles of the physical coding sublayer(PCS)and physical mediu m attachment(PMA).Aiming at the 400GbE PAM4 wireline transmission link,this dissertation constructs a link simulation platform based Input/Output Buffer Informat ion Specification(IBIS)model and Algorithm Module Interface(AMI)e xtentend model,which takes into account many non-ideal loss factors such as device package,jitter and corsstalk.On this basis,by simulating the bit error rate(BER)performance,the signal integrity problem of PA M4 serial link is analyzed,and the impro ment effect of Forward Error Correction(FEC)on link performance is a lso carefully evaluated,which show that FEC can provide a ma ximu m coding gain of 7.25d B at bit error rate of 10^-15,providing a theoretical and design foundation for subsequent chapters.Aiming at the error propagation phenomenon of decision feedback equalizer(DFE)in NRZ/PAM4 high-speed wire line transmission link,this dissertation establishes the burst error cumulative probability distribution model as a function of burst error length based on the principle of DFE error propagation.And then the probability distribution formula of error propagation under different equalization configuration s is derived to analyze and evaluate the impact of DF E error propagation on link performance.Based on this model comb ining with the actual channel,the effect of different length burst error on BER performance is simulated.The results show that the theoretical analysis es are consistent with the simulation results.In order to further enhance the error correction capability of FEC in 400GbE wire line transmission link,this dissertation analyzes various FEC interleaving schemes suitable for h igh speed link and proposes an effective pre-interleaving bit mult iple xing scheme fro m a compromise perspective of FEC symbol error probability,BER performance and hardware comp le xity,which can realize an interleaving gain of about 0.32d B@BER=10^-7,providing theoretical guidance for the design of400GbE physical interface.This dissertation designs a high-performance analog adaptive decision feedback equalizer(DFE)using 0.18?m CMOS technology to adapt automatically to the change in the transmission channel.In order to achieve the high speed and the low power cons umption,half-rate structure is adopted in the DFE main c ircuit.And least mean square(LMS)adaptive circuit based analog method is realized with mult iplie rs and integrators.The better compromise between convergence characteristics,stability and error aspect is realized by optimizing the parameters and layout of analog LMS circuit.Measurement results show that when the adaptive circuit is turn on DFE can effectively compensate 12d B channel loss at Nyquist frequency of 4GHz,whose vertical opening and horizontal opening reach 275.5 m V and 72 ps,respectively,which are significantly better than that when the adaptive circuit is turn off.For 400GbE,this dissertation designs an interleaver with parallel PRBS and CPPLL with high speed and low jitter in the physical interface PHY.In order to improve the speed of PRBS generator,this dissertation designs a40-lane paralle l PRBS generator by parallelizing the characteristic polynomia l of PRBS31 and logical expansion.And a row-column interleaver with 32 rows and 40 colu mns is realized with a shift register.For CPPLL,Phase-Frequency detector(PFD)adopts a structure with dynamic+AND gate to improve the speed and linear range by reducing the range of the blind zone as much as possible while eliminating the dead zone.In the charge pump circuit(CP),the gain boosting technology combining the cascade structure is employed to increase the output resistance,and the symmetrical signal transmission path is aslo adopted,thereby reducing the current mismatch.The voltage-controlled oscillator(VCO)adopts a complementary cross-coupled LC resonant network with top current bias to achieve a large tuning range while ensuring good noise performance.In addition,the low-speed divided-by-2 frequency divider adopts the dynamic latch structure with pull-up PMOS to reduce power consumption,and the high-speed divided-by-2 frequency divider adopts the SCFL latch structure to meet the requirement of high self-resonance frequecy.Measurement results show that the read and write clock frequency of the PRBS interleaver can reach 1.3 GHz,and the signal rate reachs 40 Gb/s.The locking range of the CPPLL is10.6?12.5 GHz,the peak-to-peak jitter and RMS jitter are 6.6ps and 886.2fs,respectively,and the power consumption is 55.2m W at the supply voltage of 1.2V.Finally,this dissertation designs a 25 Gb/s 16:1 multip le xer using 65nm LP technology.In the 16:1mult iple xe r,the high-speed multiple xing unit adopts CML logic circuit,and a CM OS logic circuit with low power consumption and a multi-phase clock mechanism eliminating redundant flip-flops are adopted in the low-speed mult iple xing unit,achieving the good compromise between speed and power consumption.Meanwhile,CMOS-CM L logic conversion adopts transmission gate and cross-coupled CMOS inverter to make the waveform more symmetrical,suppressing common mode noise.Simulation results show that the horizontal opening of output signal reachs 0.91UI,and the power consumption is 32.7 m V.This dissertation focuses on the research of high-speed wirline transmission and realted transceiver chips,which has an important theoretical and practical significance for the application of high-speed Ethernet.The research results obtained have filled the gap in the domestic research on serial link signal integrity to a certain extent,and have effectively promoted the development of domestic high-speed wire line communication and integrated circuit design.