Design Of Physical Coding Sublayer Based On PCIE 3.0 Protocol

Peripheral Component Interconnect Express(PCIe)as the third-generation high-speed serial IO bus,compared with the previous bus,can achieve a very high transmission rate at a lower cost.The PCIe bus is replacing the remaining buses as the local bus industry standard and is widely used in the field of computers and communications.The PCIe bus uses a 3-layer architecture,with the physical layer as the bottom layer,which can be further subdivided into a Physical Code Sub-layer(PCS)and a Phycial Media Attachment(PMA).As the digital logic part of the physical layer,the PCS layer realizes the logical processing of the transmitted data by the physical layer,and plays an important role in the design of the PCIe system.Based on the PCIe3.0 protocol,this thesis has designed a PCS circuit that supports 8GT/s transmission rate,and also supports 5GT/s and 2.5GT/s transmission rates,and is backward compatible with PCIe 2.0 and PCIe1.0 protocol.Based on a comprehensive study of the PCIe protocol,this article introduces the PCIe bus principle,including topology,transaction type,and device level,and focuses on the physical layer principle.According to the direction of data transmission,it is developed from both the sending and receiving paths.The following design is used as a bedding.The overall PCS circuit is divided into three major structure:data structure,clock structure and reset structure.The main functions and features of the PCS layer are summarized as:16-bit internal processing data width,configurable PIPE interface data width,8b/10b and 128b/130b codec,data boundary alignment,elastic buffer for clock offset compensation and support Loopback.Adopt VCS+Verdi combined simulation debugging software,use UVM verification platform to verify the function of main modules,and build a system verification platform based on commercial VIP for overall transmission verification.Use Design Compiler comprehensive tool,SMIC 40nm CMOS process,at 500MHz clock frequency,synthesize the circuit.At the voltage of 1.1V and the temperature of25?,the circuit area is 16935?m~2,and the power consumption is 2.99mW.Based on the actual application,three test schemes are proposed,and the Pseudo-Random Binary Sequence(PRBS)is used to test the transmission error rate.Software simulation results show that the design meets the requirements of PCIe 3.0 protocol.The PCS layer circuit can be combined with a PMA layer to form a discrete physical layer chip,which can be applied to PCIe related equipments.