Design And Implementation Of High Speed Data Acquisition System Based On PCI-Express Bus

High speed data acquisition systems are widely used in many fields,such as unmanned aerial vehicle intrusion detection,radar signal processing and biological spectrum analysis.With the continuous improvement of signal acquisition rate and processor performance,high-speed data acquisition system needs higher and higher data transmission rate to transmit large field data to the computer for processing.Therefore,it is of great significance to design a data acquisition system with high bus transmission rate.Compared with the traditional bus,PCI-Express bus not only has faster data transmission speed,but also has good compatibility and scalability,so designing high-speed data acquisition system based on PCI-Express is of great significance.In this paper,a high-speed data acquisition system based on PCI-Express bus is studied.Cache controller with continuous read and write and PCI-Express bus transmission controller design with cascaded structure are implemented,which achieves efficient cache and high-speed reliable transmission of system data.The main work of this article is as follows:1,the system design plan,including hardware and firmware control logic architecture is discussed,and two design difficulties in firmware design(efficient cache controller design and efficient PCI-Express bus transmission controller)and high-speed circuit design this one difficulty in hardware design are analyzed.2,the FPGA firmware control logic is designed and implemented,including the ADC controller,the DDR3 controller,the PCI-Express bus transmission controller and the FIFO design.Through continuous read and write mode,the DDR3 controller is designed to achieve efficient data cache,and the PCI-Express bus transmission controller with cascade DMA interface is designed to achieve high-speed data transmission.3,the ADC acquisition sub board with low delay output is designed and implemented.The schematic diagram and PCB design of ADC acquisition sub board around ADC chip are carried out,and the crosstalk and delay problem of parallel digital signal is solved through the equal length snake line in PCB design.4,function for the system is tested:design the test plan of the system and build the hardware and software testing platform,complete the hardware state test of the system,and on this basis,carry out the system acquisition function test,system cache read and write test and system transmission function experiment.The experimental results show that the system has reached the highest transmission rate of 3.3GB/s with PCI-Express 2.0 x8 channels,which reached design requirements,and the operation of system is stable and reliable.