Design And Implementation Of A High-speed Data Acquisition System Based On PCI Express Bus

With the development of technology in observing the earth from space to full-spectrum, high-resolution and all-weather, the collected remote sensing data and the code rate is mounting. In order to ensure the space ground application system able to process and display the remote sensing image in real-time, a high-speed data receiving and processing system with high-performance is necessary. However, acquisition and record of high-speed data is one of the key technologies.Based on the survey of domestic and international research on the relevant area, this paper implement the high-speed data acquisition system based on PCI Express bus, which is the I/O interconnection of third era. In the meanwhile, taking the performance and cost into account, we decided to realize the PCI Express bus interface with the dedicated bus protocol chip PEX8311.With modularized design frame of the whole system, the hardware system is mainly divided into four modules, such as differential data receiver, data buffer, PCI Express bus interface and local bus control logic. There, the high-speed PCB design of PCI Express bus interface and the timing logic of local bus are the emphases and difficulties of the whole hardware design.The system software development includes device driver and user application. Based on the WDM driver model, device driver is developed by DriverStudio develop kit, which provide perfect and powerful function. Owning to multi-thread and asynchronous I/O operations, the application is not only strengthening the interaction with user, but greatly improving data processing.At the first stage, emulation and verification is carried out, icluding high-speed signal integrality and programmable logic. Furthermore, in order to evaluate the system performance, such as BER, signal quality and circuit impedance is debugged with real-time digital oscilloscope and TDR sampling oscilloscope. Last but not least, some problem occrued in the test and the corresponding measure is discussed in detail.Finally, both the function and performance of this high-speed data transmission system has been tested under a closed-loop test environment. The test result shows that this system can deal with a real-time data stream up to 320Mbps, which has satisfied the application requirement. Besides, owing to local logic controller FPGA, the system can also be applied to other high-speed data acquisition and processing project with much more universality and flexibility.