Design And Implementation Of High Speed Data Acquisition And Transmission System Based On PCI-Express 3.0

With the development of radar technology and computer technology,modern radar systems have complex functions such as target recognition and SAR imaging,it's a trend to transmit massive data to computers for processing complex algorithm through high-speed acquisition systems.When the system receiving radar echoes,it directly samples the intermediatefrequency(IF)near the radio frequency(RF)front-end and then digital down conversion(DDC)and reduces the speed,so as to reduce the pressure of subsequent processing and transmission of the system.In the computer transmission bus,the PCI-Express bus is widely used in the interconnection of high-speed components in computer systems because of its advantages,e.g.high bandwidth and high expansion capabilities.Therefore,the PCI-Express bus is of important application significance as the transmission bus of the high-speed data acquisition system.In this thesis,a high-speed data acquisition and transmission system based on PCI-Express 3.0 bus is studied under the FPGA+CPU heterogeneous hardware platform.In the acquisition card with FPGA as the core,the DDC preprocessing is first performed on the received signal to reduce data speed,then it is cached in DDR3 using ping-pong cache management,and finally the host computer realizes the high-speed data transmission function between the acquisition card and the computer through the PCI-Express bus.The main work in the thesis is as follows: 1.Researched the construction of high-speed data acquisition and transmission system,according to the design requirements,carried out module planning of the overall structure for the system.Introduced the theoretical basic knowledge required of the system,mainly including data acquisition,DDC principles and PCI-Express bus protocol.2.Designed a high-speed data acquisition card with FPGA as the core,discussed the principle design and chip selection of each module in the card,and introduces precautions such as layout,stacking and high-speed signal routing in PCB design.3.Designed and implemented the FPGA logic program of the system acquisition card.The logic design of the ADC converter,DDC,DDR3 ping-pong cache,and PCI-Express bus module are discussed in detail.And the main functions designed in the module are simulated,logic function simulation has verified the correctness of the digital logic design by analyzing the simulation timing diagram.4.The host software of the system is designed and implemented,the scheme of design and implementation is introduced in modules,including under Windows system the PCI-Express bus driver,control program and the man-machine interface based on MFC.At the end of the thesis,the test environment of the system was built,and the evaluation board was used to verify the function of the host software and FPGA logic program.The test data shows that under the condition that the front-end data sampling rate is 2Gsps and the IF signal bandwidth is 1GHz,the 8-channel parallel filter architecture can complete the DDC function in real time at the 250 MHz clock frequency.The system transmission rate based on PCI-Express 3.0 x8 channels can reach more than 4700MB/s,which meets the high-speed transmission requirements of the system.