Research On High-Speed Data Exchange Technology With PCI Express Based On FPGA

The content of this paper is a part of the key project of the National Natural Science Fund of China "New Theory and Key Technology of Ship Radio Positioning based on AIS" (NO.61231006), which uses the technical architecture of software receiver to realize AIS base band signal processing. This research realizes the design of high-speed data transmission interface in the project. The high-speed data is I/Q demodulated data by FPGA, which is down-convert radio frequency signal after high speed AD sampling. The real-time data is transmitted to the software platform in PC, and the data transfer rate is 931.84Mb/s. As the research achievement will be used in industry, the PCI Express bus is used in this research to meet the stability of design and the requirement of high-speed data transmission. According to the performance of PCI Express bus and the cost of implementation, this research uses the PCI Express 1.1 protocol to implement high-speed data transmission. This research includes the following contents.(1) The topology structure of PCI Express system and the hierarchy structure of PCI Express bus are researched to complete the design of top-level structure of the system. The design is divided into three parts:transaction layer, data link layer and physical layer. At the same time, the system clock is determined.(2) The implement method of all levels of PCI Express endpoint is researched to design the module function of all levels. The research implements 2.5Gb/s data transfer rate at one direction, and realizes the flow control protocol of transaction layer, the Ack/Nak link transmission protocol of data link layer and the link training and initialization function of physical layer by using the RTL coding, which ensures that the data transmission is correct.(3) The whole design is tested. The function of all modules based on the FPGA is tested by Modelsim SE 6.5 simulation platform, which verifies the logic and function of this design; The reasons of timing violations are founded by analyzing the critical path of the design, and the research meets the requirements of the timing sequence by using timing constraint and timing optimization. At the same time the hardware verification is achieved, the research meet 2.5Gb/s data transfer rate.