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A Research Of Image Acquisition And Transmission Technology Based On Cache

Posted on:2016-03-29Degree:MasterType:Thesis
Country:ChinaCandidate:X X RenFull Text:PDF
GTID:2348330542976219Subject:Optical engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of image acquisition and transmission technology,a large amounts of digital information has been spread in the fields of scientific research,military,communications,digital products,machine vision and so on.So in order to solve the problem of image data storage and capacity,our design select DDR3 SDRAM to store image data;considering of the time control,FPGA has a lots of resources and high clock frequency,It can quickly and effectively control complex combinational logic and sequential logic circuit.So this subject adopts FPGA and DDR3 SDRAM combined to design.The design of image acquisition and transmission technology is studied in this paper focuses on the model of the DDR3 SDRAM memory MT18JSF25762AY-1G1.The product is launched by micron company.In this paper,the main contents of the study include the design of hardware and software.Firstly,our paper focuse on MT18JSF25762AY-1G1 device,to introduce device working process,working principle and time sequence in detail.Then from the hardware and software to describe the process.In terms of hardware,considering of the storage speed,bandwidth,amounts of data and complexity of the design,we choose DDR3 SDRAM and Cameralink.and analysis the overall structure of the program,select the main devices.Then introduce the design of FPGA circuit,CMOS image sensor driver circuit,DDR3 SDRAM interface circuit and Cameralink interface circuit design and so on.In the aspect of software,it introduced the application background and development environment,the design of DDR3 SDRAM controller is introduced in detail,and mainly use Altera’s high speed memory interface program design ATLMEMPHY to realize the design of DDR3 IP core.In addition this subject complete the design of Cameralink and CMOS image sensor,complete the design of user logic and adopts the on-chip FIFO to solve the problem of speed matching and cross clock amoang the datas transfer.Finally,Based on JESD79-3A standards.Analyzes the realization of the principle of the large capacity data storage to low speed device.
Keywords/Search Tags:DDR3 SDRAM memory, CMOS sensor, FPGA, Cameralink
PDF Full Text Request
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