Soc Low Power Design Methodology Research

With the development of IC fabrication techniques, the speed and integrity of the chip increase greatly, cooling problem has become the main factor that affecting the design reliability and package cost. So low power design has being a key technique in modern chip design, such as PDA, mobile phone, DV has much demand in low power and has greatly promoted the research and development.This paper investigates the application of low power techniques in IC design. First based on the analysis of the IC power consumption, then various low power techniques which from technics level , logic circuit level, synthesis level and physical level are given, such as clock gating, multiple Vt, multiply voltage supply and power gating. And focus on multiply voltage supply and power gating design method. As the power consumption of CMOS integrated circuits is proportional to the square of the voltage, multiply voltage supply technique becomes a most effective low power technique. And shut off power of some idle module ( power gating technique) also can decrease power consumption effectively.The library related those common low power methods is introduced in this paper. Especially Synopsys data and layout of clock gating cell, level shifter cell, isolation cell and power switch cell .Finally, based on SOC Encounter CPF low power design flow, the paper most introduced multiply voltage supply, multiply Vt, power gating design method. the implementation of a test case with those methods are present, and multiply Vt and power gating design method results are evaluated, about 40% power consumption is saved.