Design Of A Hybrid 11T SRAM Cell Based On TFET And MOSFET Devices

The feature size of Metal-Oxide-Semiconductor Field Effect Transistor(MOSFET)keeps decreasing with the scaling rule,which leads to the deterioration of its sub-threshold swing and current-switching ratio.The Static Random Access Memory(SRAM)cell composed of MOSFET has high static power consumption,which hinders its application in low-power devices.The Tunnel Field-Effect Transistor(TFET)has the advantages of low subthreshold swing,extremely low leakage current,and good current-switching ratio,which has become a substitute for MOSFET devices in low-power SRAM designs.However,TFET devices have problems such as generating forward P-I-N currents that are not controlled by the gate when the source-drain voltage difference is less than zero,and the conduction ability becomes weak when stacked,which hinders the application of TFET devices in low-power SRAM.In this paper,an 11 T SRAM cell circuit based on TFET and MOSFET is designed.The cell circuit can make full advantage of TFET devices.At the same time using MOSFET devices can avoid the problem of forward P-I-N current in TFET devices.So the static power consumption of SRAM is reduced and the stability of SRAM is increased.In addition,the SRAM cell can avoid the half-selection problem in memory array with bit interleaved structure.Finally,in order to solve the problem of weak conduction ability when TFET devices are used in stacking,this paper adopts write assist technology to enhance the writing ability of SRAM.In terms of performance,the proposed 11 T SRAM cell is simulated and compared with some typical TFET SRAM cells under different power supply voltages.The results show that at 0.8V supply voltage,the hold and read static noise margin of the proposed 11 T SRAM cell are increased by 48% compared with source external 6T TFET SRAM cell and7 T TFET SRAM cell.The write static noise margine is 39% higher than source external 6T TFET SRAM cell and 7T TFET SRAM cell,and 75.7% higher than 10 T TFET SRAM cell.In terms of reading speed,the source external 6T TFET SRAM cell and 7T TFET SRAM cell are affected by the size of the storage array,while the reading speed of the propoesd11 T SRAM cell is not affected by the size of the storage array.In terms of writing speed,the proposed 11 T SRAM cell has 27.8% higher than 10 T TFET SRAM cell.In terms of power consumption,the static power consumption of the proposed 11 T SRAM cell is similar to the10 T TFET SRAM cell,and 5 orders of magnitude lower than source external 6T TFET SRAM cell and 7T TFET SRAM cell.The reading and writing consumption are also better than other SRAM cells.It can be seen that the proposed 11 T SRAM cell achieves low-power design goals and enhances the writing capability and stability of the cell.