Design And Research Of SRAM Memory Cell Based On 22nm Low Voltage

Since the 21st century,the continuous development of Internet of things,big data and cloud computing has brought impetus to the reform of embedded memory,especially SRAM.The demand of high stability and low power consumption of mobile terminal impels people to study SRAM technology in lower voltage environment.However,the read-write ability of the minimize SRAM memory cell decreases rapidly under low voltage,and the impact of process fluctuation under advanced technology is more and more serious.The traditional 6-transistor(T)memory cell structure can not meet the stability requirements of advanced technology.Therefore,starting from the commonly used 6-transistor memory cell structure,based on the 22 nm process standard,the design and implementation of SRAM memory cell under low voltage are carried out,and the simulation results are given to verify.In terms of main work content,this paper first analyzes the basic working principle of traditional 6T memory cells and the limitations of working in low voltage environment,and gives the main indicators and measurement methods of 6T memory cell performance evaluation.Secondly,the optimization methods of SRAM bitcell are summarized.In the aspect of bitcell circuit structure,the structure of cutting off the power supply and the inverter feedback loop can improve the write ability of the bitcell.The method of adding additional word line control signal is helpful to improve the data stability of the half selected cell.The circuit structure of reading and writing separation improves the data retention ability of the bitcell when reading.In the aspect of read-write auxiliary circuit,the word line enhancement method of read-write auxiliary circuit enhances the driving ability of the transmission tube and improves the reading speed.The negative bit line voltage method of write auxiliary circuit can improve the writing ability of the memory cell and help to reduce the minimum working voltage of the cell.Finally,the advantages and disadvantages of the read-write mechanism and circuit structure of 12 t memory cell are analyzed.Compared with the traditional 6T and 12 t circuit structure,the anti noise ability of the read-write opration of 12 t memory cell is stronger,the data retention ability of semi selective cell is higher,and its size is free from read-write constraints.In order to improve the storage density and write ability of 12 t memory cell,the circuit structures of 13 T and cut-off with double end read are proposed respectively The circuit structure of 14 T memory cell with broken feedback loop.The simulation and verification of SRAM memory cell based on 22 nm technology are completed in this paper.First,HSPICE software is used to complete the post simulation of the traditional 6T bitcell,and the PPA relationship between the peripheral tube construction and the customized 6T bitcell of foundry is analyzed.After the layout area of the 6T bitcell is reduced to 0.59 times,the leakage current increases to 2.06 times,and the read and write operation delay decreases to 0.83 times and 0.71 times respectively.Secondly,the layout and layout optimization of 6T,new 9t and 12 t memory cells in 22 nm process are completed by Laker software,and the post simulation work is completed.Fast Monte Carlo simulation under 6 sigma(?)process fluctuation using Solido software shows that the minimum working voltage of 12 t memory cell is 0.4V,which is 50% higher than that of 6T memory cell.In terms of stability,RSNM and WM under 0.9V supply voltage are 3.2 times and 1.78 times of traditional 6T,respectively.The read operation delay is 0.625 times of traditional6 T,the write operation delay is 15 times of traditional 6T,and the static power consumption is 15 times of traditional 6T 01 times.To sum up,12 t bitcell can work well in low voltage environment.