Design Of Low Voltage SRAM Cell Circuit Based On 28nm Process

In order to meet people's growing demand for high-performance electronic products and reduce the cost of products to maximize the benefits.The manufacturing process nodes of semiconductor continue scaling,which promotes the integrated circuit into the post-Moore era.In recent years,SOC(system on chip)technology has become the focus of the IC design industry.SRAM(static random access memory)which is a critical part of SOC chip,has been integrated into the SOC chip.High-performance SRAM memory has been the hot spot in the industry and academia research because of its indispensable applications.SRAM memory mainly includes storage array,sense amplifier,timing control circuit,decoding circuit and input and output driver module.Among them,the storage array occupies most of the entire storage system area.Its performance is critical to the SRAM storage system.With the process node and the supply voltage scaling,the device threshold voltage is getting smaller and smaller.In addition,the mismatch of threshold voltage between adjacent transistors becomes more and more obvious.It leads to worsening robustness of SRAM memory cell.When the storage cell working,reading damage,half-selected cell reading damage become more and more frequent.And,writing ability is become weak.Read and write errors will occur in storage cell.Most of the power consumption of SRAM storage system comes from the dynamic power consumption of cell operation and the static power consumption in the sleep mode.As the process node scaling,the static power consumption of the chip becomes getting bigger,even exceeds the dynamic power consumption to become the main consumption in a chip.The voltage scaling can prominently reduce static power consumption and reduce dynamic power consumption in the quadratic form.The design of SRAM at low voltage is becoming more common.And,the battery life of the portable device can be pro-longed well under the premise of ensuring cell performance.But at low voltage,the performance of SRAM cell is further deteriorated,such as the speed decline,the deterioration of stability,the error rate of soaring.Due to these challenges,the traditional cell can't meet our needs.In this paper,the importance of SRAM storage system and the challenges of SRAM cell performance in advanced process are analyzed and researched firstly.Secondly,on the basis of analyzing the working principle of traditional SRAM memory cell,the static noise margin is measured by VTC butterfly curve,word line voltage driver,bit line voltage driver and N curve method.Based on this background,the multi-optimization-method proposed by previous researchers is analyzed.Most of these design methods only optimize the read or write performance of the cell.While,the other side remains the same or has a trend of worsening.Single-ended read and write cells tend to deteriorate the read and write speed,and challenge the design of sense amplifier.Assist circuit designs often make SRAM design complex.In order to comprehensively improve the performance of SRAM memory cells.This paper proposes a novel memory cell structure that can improve the read as well as write margins.It can largely suppress the divided voltage of the "0" nodes in the read operation of traditional 6T memory cell.And,it can improve the read static noise margin(RSNM)of SRAM memory cell,thereby to enhance the read stability of the SRAM memory cell.In the write operation,the bit line voltage is used to provide cross-coupled inverter power supply voltage.Which reduces the ability to maintain"1" for a cell.It can greatly improve the write margin(WM)of the SRAM memory cell.At the same time,it is possible to optimize the anti-PVT fluctuation capability of the SRAM memory cell and reduce the minimum operating voltage of the SRAM memory cell.Based on SMIC 28nm process node simulation results,compared with the traditional 6T cell,the RSNM and WM of the proposed 10T cell achieve 2.19 times and 2.13 times improvement,respectively,at a 1.05V supply voltage.At the same time,lower failure probability in access operations is expected.Moreover,the minimum supply voltage of the proposed 10T cell achieves 59.19%compared with 6T cell.Additionally,it also shows a better tolerance to varying process variations.