Design Of Integrated Circuit Of 8-Bit High Speed DAC

Advancement in applications in the area of video and ultra-wide-band (UWB) wireless communications needs high-speed and low-to moderate-resolution data converters so that the demand of DAC with sampling frequency up to multi-GS/s has drastically increased. However, the design of ultra high speed and high performance DAC is full of difficulties and challenges, and it is one of the difficult problems to be solved in the development of next generation communication technology and HD video. Therefore, the research and design of ultra high speed DAC has broad market prospects and theoretical value.In this paper, an 8 bits high speed current steering DAC with sampling rate up to 6GSPs is designed based on BICOMS 0.13μm process. Inputs are processed firstly by digital blocks, such as decoding, synchronization and waveform shaping, before driving differential current switches. The analog circuit is designed for providing stable and matched weight current, and the current is controlled by the switch to generate a differential output voltage on the output resistance, In addition, in order to provide an accurate and stable bias for the current source array, the analog part also includes the bandgap, the voltage-to-current circuit and the low-bit current source bias circuit. In order to compromise between the complexity of the decoding circuit and the matching requirements of the current source array, the segment ratio of DAC is set to 5:8, which means 5 bits are segmented as the most significant bits(MSBs) and the left 3bits are the least significant bits(LSBs). The 5 MSBs are binary to thermometer decoded using row-column decoder. In order to reduce the delay and minimize the DNL error,3 LSBs are also use binary to thermometer decoded. The subsequent circuits comprise a synchronous latch array, driving circuit and waveform shaping block. In addition to the schematic design of the circuit, the layout of high speed DAC is well arranged. In this paper, layout structure is compact, and the length of the line is reduced, so that the time delays between high speed signals are minimized. The clock signal and the output signal lines are designed to take the shape of the tree line, to achieve high performance at high speed. The use of Quartet crossing, concentric symmetry and other symmetry technology ensure a good match.This paper optimizes the driver circuit and switch drive waveform shaping circuit. The 5-bit row-column decoder is divided into 2-bit row-decoder,3-bit column-decoder and 32 logic units. Each row-decoded signal dives 16 logic units adopting 4-oder tree line, which enhance line density and the drive capability requirements. This problem can be solved by using distributed driving blocks with redundant decoders. The signal crosstalk is effectively retrained because of the reduction of wiring density. The current switch drive circuit is well designed, In addition to meet the traditional high cross point and low swing requirements, a steep decent at the fall window of the driving signal is created, so as to improve the high frequency performance of the system. At 6GSPs clock rate, with the 2.96GHz output signal bandwidth, simulation results show that SFDR of the DAC with optimization is 34dB higher than of the DAC without optimization.Post simulation results show that the 8-bit converter can work at the sampling rate up to 6GSPs, in the entire Nyquist bandwidth. INL and DNL can be controlled within 0.15LSB and 0.2LSB. At 4GSPs clock rate, with the 1.98GHz output signal bandwidth, SFDR is 53dB, and power consumption is less than 63mW. At 6GSPs clock rate, with the 2.96GHz output signal bandwidth, SFDR is 33dB, and power consumption is less than 95mW.