Used In Serial Communication Equipment In The Research Of Low Noise Charge Pump Phase-locked Loop

Now society is the society of information exchange.Information data are constantly updated every day.How to conduct efficient communication and research of high performance communication equipment has become a hot spot now.USB2.0 communication equipment as a typical serial communication equipment has the characteristics of high speed,simple and easy to carry and it is the most widely used in people’s daily life.USB communication mode is divided into three types:low speed,speed and high speed mode.High speed mode transmission speeds of 480 Mbps.High-speed mode is the main mode of the large capacity data transmission.As the mainstream of the USB’s clock circuit module,Phase-locked loop,its performance directly affects the quality of communication.In this thesis,through a variety of noise reduction scheme,I designed a low noise,fast locking phase-locked loop that can be used very well.(1)I fully analyzed the working principle of charge pump phase-locked loop,linear model,noise model,and the ideal effect.I summarize the comparative advantages of various circuit module,appropriate low noise circuit are designed.On the basis of SMIC0.13 μm process model library,I design and optimization of the charge pump phase-locked loop circuit module.I researched the discriminator phase,the electric design crushing zone.I had low noise for charge pump circuit design.My second order loop filter are used on the loop filter.It can be fast attenuation of noise.I designed of voltage-controlled oscillator noise less difference delay unit circuit and frequency modulation bias circuit.I designed 40 times the frequency divider.It uses a divider 5 divider multiplied by 8 cascade scheme.I finally simulate the charge pump phase-locked loop.The simulation results show that the overall charge pump phase-locked loop noise performance excellence.(2)On the basic of SMIC0.13 μm process model library,I the results of the overall charge pump phase-locked loop simulation.The simulation results show:Under the power supply voltage of 1.8 V,the output of the phase-locked loop frequency range to 130 MHz to 830 MHz.Its center frequency is 480 MHZ.The scope of its voltage-controlled voltage of 0.4 V to 1.0 V.In the offset frequency 480 MHz 1 MHz frequency offset,its phase noise is 111.3 dBc/Hz.Its locking time is 3.8 μs.The whole simulation circuit performance meets the requirement of USB2.0 protocol.It reaches the expected design goal.