Design Of PLL Loop And AFC Based On 0.13?m CMOS Process

The main module of wireless transceiver system including incoming and outgoing links,and frequency synthesizers(FS),especially the frequency synthesizers is the important factors that affect the signal quality of a wireless transceiver system.For the reason that the wireless transceiver system needs to transfer the received signal from high frequency to low frequency,and transfer the low frequency signal,which need to be launched,to high frequency signal,the quality of frequency synthesizers' frequency signal has a direct effect on the signal quality of wireless data transceiver system.So the design of high performance frequency synthesizers is the key to wireless transceiver system.The main content of this paper include:do some research for the loop of phase-locked loop;research the architecture of broadband high frequency and fast locking phase-locked loop as well as design the key circuit modules of it;the design of behavioral model for phase-locked loop's some part for this design and so on.All the study of circuits in this paper are based on TSMC 0.13?m CMOS process.In this paper,at first,starting from the principles of phase-locked loop,by comparing the difference of all kinds of frequency synthesizers and in accordance with the design target,we confirmed the design structure of this phase-locked loop frequency synthesizers.Then on the basis of this research we set up the transmission model and noise model of this PLL,and according to these established models,we completed the parameter design of phase lock loop(PLL).This section aims to build a general loop parameters model for broadband high frequency and fast locking PLL,so as to provide a method for the design of this kind of phase-locked loop.To prove the rationality of PLL cycle model and parameter design,this paper established a behavior model of PLL cycle,and on the basisi of this model,we get the behacioral simulation result.From the result,we can get the lock time,lock voltage and so on of the cycle.this part aimed to prove the resonality of cycle desugn by a simple way.This paper also research the architecture of broadband high frequency and fast locking phase-locked loop as well as design the key circuit modules:AFC,of it.Then,from the principles of AFC design,we completed circuit design and simulation,then,we get the map of this digital circuit and send to tapeout.This part aimed to design the key part of broadband high frequency and fast locking phase-locked loop.