Development Of 2.5 GSPS Data Conversion Module

With the increasing number of data services in the communication system and the increasing amount of business data,the communication system is moving towards high bandwidth and high speed.Data converters(ADC and DAC),as an important module of the communication system,connecting the analog signal domain in the communication system and the digital signal domain,high sampling rate and high resolution converter can be the greatest degree of retention and reproduction of the original analog signal Information,while supporting high-bandwidth and high-traffic data transmission.The traditional high-speed converter uses LVDS interface to transmit data,the higher the resolution of the converter,the more data signal lines,the greater the complexity of the hardware connection.The new JESD204 B interface uses high-speed serial transmission of sampling data to support fewer package pins and package area,is the current converter application research hotspot.Based on the new JESD204 B interface high speed converter,this paper designs a data conversion module integrating A/D and D/A converters with the aim of versatility and flexibility.The main work of the thesis is depicted as follows:1.The hardware Design of 2.5GSPS Data Conversion Module Board: According to A/D and D/A converters,design converters peripheral circuits,including clock channel design,data channel design and power supply design.By analyzing the functional modules inside the converter,the external interface circuit of the converter is designed flexibly so that the data conversion module can be applied to different systems and is versatile.2.The JESD204 B interface design between Converter and FPGA: For the ADC,the data receive logic in FPGA should be designed;for the DAC,the data transmit logic in FPGA should be designed.By analyzing JESD204 B serial interface link synchronization process,use GTH transceiver to achieve the physical layer of the link,JESD204 IP core to achieve the link layer,and design data mapping and de-mapping logic to ensure that the interface between the converter and FPGA can normally transmit data samples.3.Multi-board synchronization design: Mainly based on the design of the data conversion module,expand its function to enable it to achieve multi-channel synchronous sampling.By analyzing the delay uncertainty between the link and the link,the clock design and the design of the internal logic clock delay to ensure the stability of the deterministic delay between the link and the link,and thus achieve the effect of multi-board synchronization.Finally,the signal integrity of the high speed channel between the converter and FPGA is simulated and analyzed,which provides a reference for the design of PCB.