Implementation Of High-Speed Frequency Hopping Based On JESD204B

Frequency hopping technology,with its excellent anti-jamming and anti-interception capabilities,has become an important communication method in modern communication.Traditional frequency hopping is based on the LVDS level interface to complete the data transmission between the converter and the programmable logic chip.However,as users' demands for data types and data volumes increase,the traditional implementation methods can no longer meet the needs.With the development of electronic information technology,CML level are used more and more in the interface of high-speed converter compared to the traditional LVDS level.And the focus of research on high-speed interface has also shifted from high-speed parallel to high-speed serial.The high-speed serial JESD204 B interface based on CML level has gradually become a research hotspot in recent years because of its Gigabit transmission rate,fewer pins,simpler PCB layout,smaller package volume and other characteristics.When JESD204 B interface works at high data rate,any delay will have a significant impact on performance.In order to overcome this problem,the protocol defines the concept of deterministic delay.In this thesis,based on the deterministic delay of the JESD204 B protocol,the programmable logic control interface is used to control the internal frequency synthesizer of the high-speed converter to complete the high-speed frequency hopping and achieve accurate frequency hopping.Compared to the traditional frequency hopping method,the transmission rate of the system is greatly improved.The main contributions of this thesis can be summarized as follows:1.Research on JESD204 B three-layer protocol: The theory of deterministic delay was studied firstly,and then the causes of system delay and the definition of deterministic delay in the JESD204 B protocol was analyzed.Based on the integrated functional modules of the high-speed converter,the basic theory of the high-speed converter was studied.2.Complete the circuit design of the system: According to the actual requirements of the system,the model was determined by comparing currently available chips.Then analog input and output interfaces were designed according to the internal circuit characteristics of the system chips.The next step is to design the clock channel according to the special requirements of the JESD204 B protocol for clock.Finally,it is the design of the system power supply according to the power consumption of each module of the system and the requirements of power sequence,etc.3.Complete the high-speed serial interface design between the high-speed converter and the programmable logic device: Based on high-speed transceiver GTH and JESD204 B IP core inside the FPGA,the design of the physical layer and data link layer was completed.And based on the data mapping relationship inside the high-speed converter,the data mapping and de-mapping of the data transfer layer logic were designed.4.Analyze the realizability of deterministic delay based on the adjusting ability of clock chips and clock routing delay: The design of high-speed frequency hopping transmit and receive links was completed firstly.Then in order to complete the test of high-speed frequency hopping,the clock delay of clock chip and the high-speed conversion chip were adjusted according to system requirements.Finally,the test results was analyzed to identify our scheme.