The Design Of The Dual Port CMOS SRAM With High Speed And Low Power

As the first transistor was invented at Bell laboratory in 1947,microelectronics technology has gotten a rapid improvement. At present, the circuits has entered the vary large scale integrate century. Microelectronics technology , as the base of the information industry,is developing rapidly in our country.Today microelectronics has penetrated into social economy and people's live.Quantities of digital products,such as mobile phone,image process, phonetic synthesize,computer and digital camera, are related with microelectronics technology. The static random acess memory (SRAM),as one member of the digital products,has made a mighty advance.The SRAM has been widely applied at computer,communication and high speed data exchange system.It is said the memory shares the 35% of the whole semiconductor market,and the SRAM is 15% of the semiconductor memory sale.Further more,the SRAM market is increasing at the rate of 10% each year.Hence the study of the SRAM,which is as the important part IC field,is significant.Dual port static memory uses two groups independent address, data and control bus, it allows different entities(such as CPU)access. Hence the access rate of the dual port memory is 2 times of the single port memory. The access rate of the memory is determined by crucial path which is between data input and data output. The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer. The memory unit is the core of the memory, whose structure is relatively fixed, and whose performance is determined by the current process. So people pay more attention to the peripheric circuits (such as decoder and sense amplifier) of the memory when they design the SRAM.A kind of 1M(128K×8Bit) dual port static random memory is designed in the article.The structure and principle of the dual port SRAM was described, in addition, the arbiration and control circuits is analyzed. The memory units, decoder and sense amplifier are designed and optimized. Furthmore, the article analyzes the reason which influences the power and rate of the memory, and provides optimization measures,which improves the ability of the whole memory by peripheric circuits. At last, the memory system is simulated by Hspice and Hsim, the results show: the access time of the memory is less than 15ns at normal work condition, the typical dynamic power is 150mA, and static power is 50mA. The design has achieved all its goal. Hence, the memory designed is high speed and low power at the same process, which can be used for reference of the memory design in the future.There are five chapters in the article. The first chapter introduced the development and structure of the memory; The second chapter described the design and optimization of the decoder; The third chapter is about the design of the sense amplifier; The design of memory units is in the fourth chapter; The five chapter discussed the arbiration and control circuits; The conclusion and improvement is given in the last chapter.