Architectural explorations for high-performance field-programmable gate arrays

Cell-based design technology has dominated ASIC implementation over the past quarter century by offering an economically compelling combination of low manufacturing cost and acceptable design and prototyping costs. With the advent of sub-100nm CMOS technologies, the design and prototyping costs of cell-based implementation have become prohibitive for most ASICs, making FPGAs increasingly popular. Current FPGAs, however, cannot meet the performance requirements of many ASICs due to their high programming overhead. Therefore, designing high-performance FPGA architecture is becoming increasingly important.;This thesis presents several architecture studies aimed at improving FPGA performance. We first present our work on performance benefits of monolithically stacked 3D-FPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and interconnects, are investigated. A Virtex-II style 2D-FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3D-FPGA. It is assumed that only the switch-transistor and configuration memory cells can be moved to the top layers and that the 3D-FPGA employs the same logic block and programmable interconnect architecture as the baseline 2D-FPGA. Assuming a configuration memory cell that is ≤ 0.7 the area of an SRAM cell and switch transistor having the same characteristics as nMOS devices in the CMOS layer are used, it is shown that a monolithically stacked 3D-FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2D-FPGA fabricated in the same 65nm technology node.;Based on lessons learned from the previous study, we embarked on two architectural studies to further improve performance of 2D-FPGA. The first is a new low-power routing fabric and shows that an FPGA that uses this fabric can achieve 1.54 times lower dynamic power consumption and 1.31 times lower average net delays with only 8% reduction in logic density over a baseline island-style FPGA implemented in the same 65nm CMOS technology. These improvements in power and delay are achieved by (i) using only short interconnect segments to reduce routed net lengths, and (ii) reducing interconnect segment loading due to programming overhead relative to the baseline FPGA without compromising routability. The new routing fabric is well-suited to monolithically stacked 3D-IC implementation. It is shown that a 3D-FPGA using this fabric can achieve a 3.3 times improvement in logic density, a 2.46 times improvement in delay, and a 2.87 times improvement in dynamic power consumption over the same baseline 2D-FPGA.;The second study is a design tool for routing channel segmentation in island-style FPGAs. Given the FPGA architecture parameters and a set of benchmark designs, this tool optimizes routing channel segmentation using the average interconnect power-delay product as a performance metric, which is estimated from placed and routed designs. A simulated-annealing procedure is used, whereby segmentation is incrementally changed in each iteration, the benchmark designs are mapped using VPR, and the performance metric is computed to decide whether to accept or reject the new segmentation. Run time is significantly reduced by using incremental routing in each iteration and parallelizing the metric evaluation. Experimental results using the MCNC benchmark designs demonstrate an average of 22% and 15% reduction in delay and power relative to a baseline segmentation. The results also show that average segment length should decrease with technology scaling. Finally, we demonstrate how the TORCH tool can be used to optimize other aspects of programmable routing in an FPGA.