Study And Design Of Two Port High Speed And Low Consumption SRAM

With the high-speed development of integrated circuits,the performance of the CPU on SOC Chips is rising rocketly as well.However,as the SRAM memory which is integrated on SOC develope in a speed that is obviously slower than that of CPU,the performance of SRAM is gradually becoming the drawback of the development of SOC chips.On the other hand,the leakage current of SRAM is also another question induced by the shrinking of the tech node of integrated circuits,which leads to growing rate of static power consumption.To solve the problems mentioned above,this article has designed a high-speed and low-consumption SRAM memory with volume of 320x128bit.This article has compared different SRAM memory cells-4T2R,6T and 8T cell,and chose 8T cell at last as the basic cell of the SRAM that designed this time,for its separate read and write path,avoiding read-disturb issue and a little larger area however.And then we chose the two-port SRAM structure because its smaller area and similar speed comparing to the dual-port SRAM.As the basic cell and SRAM structure have beed desided,this article designed the timing-adjustable replica bit line,based on the self-timing mechanism of SRAM and the replica bit line technology.To help the SRAM out of the far too large leakage power,three modules were designed:gate-control address decoder,CLK generator and low-leakage WL driver,all controlled by the data holding signal-DH.And also a stacking BL structure based on cascading transistors is proposed to control the leakage power.Meanwhile,the SRAM memory array has been split accordingly,then the WL.To higher up the SRAM working efficience and save the power consumption,an address decoder and data output driver are design accordingly.After the finish of the circuit structure,a layout is drawed.The analysis of the overall function and the function of timing-adjustable replica bit line is carried out based on the layout and the functions simulated are all successful.With the netlist that are constracted out of the layout file,the EMIR analysis is done with the EM rate reached above80%,which just reach the international standard of IC design.And all the similation and analysis all proved the success working and the achievability of the SRAM that is designed in this article.This SRAM is fullfilled with the 7nm tech node of TSMC.It can work under the voltage of 0.6～1V,under the sequency of 1.5～3GHz,under the temperature of-40～125℃,with a layout that occupies 4887.2um~2.Comparing to the SRAM with the same volume that are automatically generated by business software,it occupies 15%more area,whilet with 22%higher working speed and 37.3%lower static power consumption.