| Due to the advantages of small cell size,large capacity,and high durability,DRAM is widely used in fields such as mobile devices,servers,and PCs.Its market size exceeds 60 billion U.S.dollars,accounting for more than one-tenth of the globally integrated circuit market.With the progress of the process,the size of the DRAM capacitor continues to decrease,which brings a huge challenge to the voltage difference between the SA identification bit lines.Affected by random doping fluctuations,the offset voltage of SA gradually increases,so the research on DRAM low-offset sensitive amplifiers is very meaningful.This paper first introduces the structure and theory of DRAM,and then analyzes the causes of SA offset voltage,as well as the theory and merit and demerit of two kinds of low offset SA.Through the analysis of the existing structure,this paper proposes a capacitive offset compensation sensitive amplifier.On the one hand,this solution adds a capacitor for offset compensation and isolates the bit line from the sense amplifier through the transmission tube,so that the offset compensation and the bit line precharge do not affect each other.It can realize offset compensation and pre-charging at the same time,thereby improving the speed of the sense amplifier.On the other hand,this circuit uses a small capacitor for offset compensation instead of a large capacitor such as a bit line capacitor,so it reduces power dissipation compared to other solutions.Based on the 65 nm process node,under the power supply voltage of 1.2V,the bit line capacitance of 100 f F,and the TT process corner,the proposed SA reduces the offset voltage by38% compared with OCSA,reduces the power consumption by 50.17%,and increases the speed by 16.5%;and in the FF process corner-25 ℃,SS process corner 85 ℃,FS process corner25 ℃,SF process corner 50 ℃ simulation,the offset voltage is reduced by 21.7%-41.4%;also,because the design of the sense amplifier uses an independent capacitor as the offset voltage storage The unit avoids the impact on the performance of the sense amplifier due to the different bit line capacitance.Compared with OCSA,the power consumption is reduced by46%-55.6% and the speed is increased by 13.3%-26.2% under different bit line capacitance.Similarly,under the power supply voltage of 1.2V,the bit line capacitance of 100 f F,and the TT process corner,the proposed SA reduces the offset voltage by 27.5% and the power consumption by 29.1% compared with the OMCSA,which further verifies the effectiveness of the design in this paper. |
